AP64350SP-13 Diodes Incorporated

Request Datasheet AP64350 3.8V TO 40V INPUT, 3.5A LOW IQ SYNCHRONOUS BUCK WITH PROGRAMMABLE FREQUENCY Description Pin Assignments The AP64350 is a 3.5A, synchronous buck converter with a wide input TOP VIEW voltage range of 3.8V to 40V. The device fully integrates a 75m high- side power MOSFET and a 45m low-side power MOSFET to provide high-efficiency step-down DC-DC conversion. BST 1 8 SW The AP64350 device is easily used by minimizing the external component count due to its adoption of peak current mode control. VIN 2 7 GND The AP64350 design is optimized for Electromagnetic Interference EXPOSED PAD (EMI) reduction. The device has a proprietary gate driver scheme to 9 resist switching node ringing without sacrificing MOSFET turn-on and EN 3 6 COMP turn-off times, which reduces high-frequency radiated EMI noise caused by MOSFET switching. AP64350 also features Frequency Spread Spectrum (FSS) with a switching frequency jitter of 6%, which reduces EMI by not allowing emitted energy to stay in any one RT/CLK 4 5 FB frequency for a significant period of time. The device is available in an SO-8EP package. SO-8EP Features Typical Application Circuit INPUT VIN 3.8V to 40V VIN BST 3.5A Continuous Output Current C3 L 100nF OUTPUT 5.5H 0.8V 1% Reference Voltage VOUT EN SW 5V C4 R1 22A Low Quiescent Current (Pulse Frequency Modulation) OPEN 115k AP64350 C1 C2 FB Programmable Switching Frequency: 100kHz to 2.2MHz 10F 2 x 22F R2 22.1k External Clock Synchronization: 100kHz to 2.2MHz RT/CLK COMP Up to 85% Efficiency at 5mA Light Load RT R5 200k 14k GND C6 Proprietary Gate Driver Design for Best EMI Reduction 47pF C5 (Optional) 3.3nF Frequency Spread Spectrum (FSS) to Reduce EMI Low-Dropout (LDO) Mode Precision Enable Threshold to Adjust UVLO Protection Circuitry VOUT = 5V, L = 5.5H VOUT = 3.3V, L = 4.7H o Undervoltage Lockout (UVLO) o Output Overvoltage Protection (OVP) 100 90 o Cycle-by-Cycle Peak Current Limit 80 o Thermal Shutdown 70 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) 60 Halogen and Antimony Free. Green Device (Note 3) 50 40 30 20 10 0 0.001 0.010 0.100 1.000 10.000 IOUT (A) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See Request Datasheet AP64350 Pin Descriptions Pin Name Pin Number Function High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel power MOSFET. A 100nF BST 1 capacitor is recommended from BST to SW to power the high-side driver. Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a VIN 2 3.8V to 40V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching of the IC. See Input Capacitor section for more details. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to EN 3 turn it off. Connect to VIN or leave floating for automatic startup. The EN has a precision threshold of 1.18V for programing the UVLO. See Enable section for more details. Resistor Timing and External Clock. This pin can be used to control the switching frequency by setting the internal oscillator frequency or by synchronizing to an external clock. Connect a resistor from RT/CLK to GND to set the internal oscillator frequency. An external clock can be input directly to the RT/CLK pin and the internal oscillator RT/CLK 4 synchronizes to the external clock frequency using a PLL. If the external clock edges stop, the operating mode automatically returns to resistor frequency programming. See Programming Switching Frequency section for more details. Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output. FB 5 See Setting the Output Voltage section for more details. Compensation. Connect an external RC network to the COMP pin to adjust the loop response. See External Loop COMP 6 Compensation Design section for more details. GND 7 Power Ground. Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter SW 8 from SW to the output load. EXPOSED Heat dissipation path of the die. The exposed thermal pad must be electrically connected to GND and must be 9 PAD connected to the ground plane of the PCB for proper operation and optimized thermal performance. Absolute Maximum Ratings (Note 4) (At T = +25C, unless otherwise specified.) A Symbol Parameter Rating Unit -0.3 to +42.0 (DC) VIN Supply Pin Voltage V -0.3 to +45.0 (400ms) V Bootstrap Pin Voltage V - 0.3 to V + 6.0 V BST SW SW V Enable/UVLO Pin Voltage -0.3 to +42.0 V EN RT/CLK Pin Voltage -0.3 to +6.0 V V RT/CLK Feedback Pin Voltage -0.3 to +6.0 V V FB V Compensation Pin Voltage -0.3 to +6.0 V COMP -0.3 to VIN + 0.3 (DC) Switch Pin Voltage V V SW -2.5 to VIN + 2.0 (20ns) Storage Temperature -65 to +150 C T ST T Junction Temperature +160 C J T Lead Temperature +260 C L ESD Susceptibility (Note 5) HBM Human Body Model 2000 V CDM Charged Device Model 500 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above may cause permanent damage to the device. These are stress ratings only functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. 2 of 5 October 2019 AP64350 Databrief Diodes Incorporated www.diodes.com