AP7175SP-13 Diodes Incorporated

NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART AP7175 3A ULTRA LOW DROPOUT LINEAR REGULATOR WITH ENABLE Description Pin Assignments (Top View) The AP7175 is a 3.0A ultra low-dropout (LDO) linear regulator that features an enable input and a power-good output. 1 8 GND EN The enable input and power-good output allow users to configure 2 7 PG FB power management solutions that can meet the sequencing V 3 6 V OUT CNTL requirements of FPGAs, DSPs, and other applications with different start-up and power-down requirements. 4 5 V V OUT IN The AP7175 features two supply inputs, for power conversion supply SO-8EP and control. With the separation of the control and the power input (Top View) very low dropout voltages can be reached and power dissipation is 1 8 EN GND reduced. 2 7 PG FB A precision reference and feedback control deliver 1.5% accuracy V 6 V OUT 3 CNTL over load, line, and operating temperature ranges. V 4 5 V OUT IN MSOP-8EP The AP7175 is available in SO-8EP and MSOP-8EP package with an exposed PAD to reduce the junction to case resistance and extend the temperature range it can be used in. = PAD (connected to VIN) Features Applications V Range: 1.2V to 3.65V V 3.0V to 5.5V IN CNTL Notebook Adjustable output voltage PC Continuous Output Current I = 3A OUT Netbook Fast transient response Wireless Communication Power on reset monitoring on V and V CNTL IN Server Internal Softstart Motherboard Stable with Low ESR MLCC Capacitors Dongle Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Front Side Bus VTT (1.2V/3.3A) Halogen and Antimony Free. Green Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART AP7175 Pin Descriptions Pin Number Pin Function Name SO-8EP MSOP-8EP GND 1 1 Ground FB 2 2 Feedback to set the output voltage via an external resistor divider between V and GND. OUT Power Output Pin. Connect at least 10F capacitor to this pin to improve transient response and V 3/4 3/4 required for stability. When the part is disabled the output is discharged via an internal pull-low OUT MOSFET. Power Input Pin for current supply. Connect a decoupling capacitor (10F) as close as possible to V 5 5 IN the pin for noise filtering. BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor (1F) as close V 6 6 CNTL as possible to the pin for noise filtering. Power Good output open drain to indicate the status of V via monitoring the FB pin. This pin is OUT PG 7 7 pulled low when the voltage is outside the limits, during thermal shutdown and if either V or V CNTL IN go below their thresholds. Enable pin. Driving this pin low will disable the part. When left floating an internal current source will EN 8 8 pull this pin high and enable it. PAD EP EP Exposed pad connect this to V for good thermal conductivity. IN Functional Block Diagram V IN Power On Reset V CNTL (POR) 5A Thermal Shutdown EN Control Logic SoftStart 0.8V Ref Error Amp 0.8V V OUT Ref Current Limit and Short Circuit FB GND PG Delay 90%V Ref POR 2 of 14 January 2017 AP7175 Diodes Incorporated www.diodes.com Document number: DS35606 Rev. 4 - 3