AP9050FDB-7 Diodes Incorporated

AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Description Pin Assignments AP9050 is designed to protect the latest generation of PMICs (Top View) for portable applications such as UMPCs, smartphones and others utilizing battery power. 1 6 8 The integrated LDO allows the PMIC to power up and 2 5 determine whether the connected power supply (USB or AC-DC wall adapter) is valid and a safe operation can be 7 performed. 3 4 The PMIC controls the operation of the integrated n-channel MOSFET to either pass the line voltage or disconnect the line U-DFN2020-6 from the PMIC to protect its internal circuits in the event of an over-voltage. The AP9050 is available in a low-profile U-DFN2020-6 package. Features Applications Power Interface for New Generation PMICs Input Supply Range from 3V to 30V Charger Front End Protection Lower Power Dissipation and Higher Efficiency as compared to a Zener Shunt Regulator Smartphone LDO is stable without a bypass capacitor on the output Cell Phone and operates across the temperature range Ultra Mobile PC Available in a U-DFN2020-6 package with a typical Tablets height of 0.575mm Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Pin Descriptions Pin Name Description 1 Source Source of the n-channel power FET. Pass-switchs output pin. 2 Gate Gate of the FET switch. Pass-switchs control pin. 3, 7 V Input voltage to the internal LDO. IN 4 Ground LDO ground connection. V 5 Output of the LDO. OUT 6, 8 Drain Drain of the power FET. Pass-switchs input pin. Functional Block Diagram Figure 2. Functional Block Diagram 2 of 9 March 2011 AP9050 Diodes Incorporated www.diodes.com Document number: DS35283 Rev. 1 - 2 NEW PRODUCT