FK Series Crystal Clock Oscillator (XO) 3.2 x 2.5mm 2.5V CMOS Low Jitter XO FK Package: 3.2 x 2.5mm Ceramic SMD Recommended Land Pattern: Product Features 1 to 156.25 MHz Frequency Range <1 ps RMS jitter 2.5V CMOS compatible logic levels Designed for standard reofl w and washing CREATED USING CADSTD LITE FREEWARE FROM WWW.CADSTD.COM. NON-COMMERCIAL USE ONLY. techniques Low power standby mode Pb-free and RoHS/Green compliant Pin Functions: Pin Function Product Description 1 OE 2 Ground The FK Series 2.5V crystal clock oscillator 3 Clock Output achieves superb stability and low power consumption over a broad range of operating 4 V DD conditions and frequencies. The low jitter output clock signal, generated internally with a non-PLL oscillator design, is compatible with LVCMOS logic levels. The device, available on tape and reel, is contained in a 3.2 x 2.5mm surface-mount ceramic package. CREATED USING CADSTD LITE FREEWARE FROM WWW.CADSTD.COM. NON-COMMERCIAL USE ONLY. Applications Part Ordering Information: Ideal for compact, high-density applications requiring low power or tight stability, including: UM XXX YYYY FK Network adapter cards YYYY = SpecificationCode Portable Multimedia Devices XXX = FrequencyCode Hard Disk Drives ProductFamily GPS/Navigation Following the above format, Saronix-eCera part numbers will be assigned upon Bluetooth confirmation of exact customer requirements. 802.11a/b/g WiFi SaRonix-eCera is a Pericom Semiconductor company US: +1-408-435-0800 TW: +886-3-4518888 www.saronix-ecera.com All specifications are subject to change without notice. FK 2.5V REV2015 1 15-0087FK 2.5V CMOS Low Jitter XO FK Series Crystal Clock Oscillator (XO) 3.2 x 2.5mm Electrical Performance Parameter Min. Typ. Max. Units Notes Output Frequency 1 156.25 MHz As speciefi d Supply Voltage 2.25 2.5 2.75 V 10 1 to 50 MHz Supply Current, Output Enabled mA 18 50 to 156.25 MHz Supply Current, Standby Mode 10 A Output Hi-Z Frequency Stability 20 to 50 ppm See Note 1 below -20 +70 Commercial (standard) Operating Temperature Range C -40 +85 Industrial (standard) Output Logic 0, V 10% V V OL DD Output Logic 1, V 90% V V OH DD Output Load 15 pF Duty Cycle 45 55 % Measured 50% V DD Rise and Fall Time 5 ns Measured 10/90% of waveform Jitter, Phase 1 to 156.25 MHz 1 ps RMS (1-) 12kHz to 20 MHz frequency band up to 75 MHz 5 Jitter, ps RMS (1-) 20.000 adjacent periods Accumulated 75 to 156.25 MHz 3 up to 75 MHz 50 Jitter, ps pk-pk 100.000 random periods Total 75 to 156.25 MHz 30 Notes: 1. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25C), aging (1 year at 25C average effective ambient temperature), shock and vibration. 2. For specifications othere than those listed, please contact sales. Output Enable / Disable Function Parameter Min. Typ. Max. Units Notes Input Voltage (pin 1), Output Enable 0.7 V V or open DD Input Voltage (pin 1), Output Disable (low power standby) 0.3 V V Output is Hi-Z DD Internal pullup resistance 50 k Output Disable Delay 100 ns Output Enable Delay 10 ms Absolute Maximum Ratings Parameter Min. Typ. Max. Units Notes Storage Temperature -55 +125 C For the latest product information visit: