FK Series Crystal Clock Oscillator (XO) 3.2 x 2.5mm 1.2V CMOS Low Jitter XO FK Package: 3.2 x 2.5mm Ceramic SMD 3.20.1 Recommended Land Pattern: Product Features 2.50.1 1 to 60 MHz Frequency Range <1 ps RMS jitter 1.2V CMOS compatible logic levels PIN 1 Designed for standard reflow and washing techniques Low power standby mode 1.00.15 Pb-free and RoHS/Green compliant Pin Functions: Pin Function 0.9 0.10 Product Description 1 OE Function 2 Ground 1 2 The FK Series 1.2V crystal clock oscillator 0.6 achieves superb stability and low power 3 Clock Output 1.6 consumption over a broad range of operating 4 V DD conditions and frequencies. The low jitter 4 3 output clock signal, generated internally with a non-PLL oscillator design, is compatible with 2.1 LVCMOS logic levels. The device, available on (Bottom View) tape and reel, is contained in a 3.2 x 2.5mm surface-mount ceramic package. Part Ordering Information: Applications A: ProductFamily FK XXX YYYY Ideal for compact, high-density applications B: XXX = FrequencyCode requiring low power or tight stability, including: C: YYYY = SpecificationCode Network adapter cards Portable Multimedia Devices Following the above format, Saronix-eCera part numbers will be assigned upon confirmation of exact customer requirements. Hard Disk Drives GPS/Navigation Bluetooth 802.11a/b/g WiFi SaRonix-eCera is a Pericom Semiconductor company US: +1-408-435-0800 TW: +886-3-4518888 www.saronix-ecera.com All specifications are subject to change without notice. FK 1.2V REV2010 MAY19 01.3 1FK 1.2V CMOS Low Jitter XO FK Series Crystal Clock Oscillator (XO) 3.2 x 2.5mm Electrical Performance Parameter Min. Typ. Max. Units Notes Output Frequency 1 60 MHz As speciefi d Supply Voltage 1.08 1.20 1.32 V 2 1 to 30 MHz Supply Current, Output Enabled mA 4 30 to 60 MHz Supply Current, Standby Mode 10 A Output Hi-Z Frequency Stability 20 to 50 ppm See Note 1 below -20 +70 Commercial (standard) Operating Temperature Range C -40 +85 Industrial (standard) Output Logic 0, V 10% V V OL DD Output Logic 1, V 90% V V OH DD Output Load 15 pF Duty Cycle 45 55 % Measured 50% V DD Rise and Fall Time 4 ns Measured 10/90% of waveform Jitter, Phase 1 ps RMS (1-) 10kHz to 20 MHz frequency band Jitter, Accumulated 5 ps RMS (1-) 20.000 adjacent periods Jitter, Total 50 ps pk-pk 100.000 random periods Notes: 1. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25C), aging (1 year at 25C average effective ambient temperature), shock and vibration. 2. For specifications othere than those listed, please contact sales. Output Enable / Disable Function Parameter Min. Typ. Max. Units Notes Input Voltage (pin 1), Output Enable 0.7 V V or open DD Input Voltage (pin 1), Output Disable (low power standby) 0.3 V V Output is Hi-Z DD Internal Pullup Resistance 50 k Output Disable Delay 200 ns Output Enable Delay 10 ms Absolute Maximum Ratings Parameter Min. Typ. Max. Units Notes Storage Temperature -55 +125 C SaRonix-eCera is a Pericom Semiconductor company US: +1-408-435-0800 TW: +886-3-4518888 www.saronix-ecera.com All specifications are subject to change without notice. FK 1.2V REV2010 MAY19 01.3 2