PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Detect Feature Features Description One high-speed PCI-Express lane Pericom Semiconductors PI2EQX4401D is a low power, PCI-Express compliant signal re-driver. The device provides Adjustable Transmiter De-Emphasis & Amplitude programmable equalization, ampli cation, and de-emphasis Adjustable Receiver Equalization by using 4 select bits, SEL 0:3 , to optimize performance One Spread Spectrum Reference Clock Buffer Output over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX4401D supports two 100 Differential Input Signal Level Detect and Output Squelch CML data I/Os between the Protocol ASIC to a switch fabric, 100 Differential CML I/Os across a backplane, or extends the signals across other distant Low Power (100mW per Channel) data pathways on the users platform. Stand-by Mode Power Down State The integrated equalization circuitry provides exibility with signal integrity of the PCI-express signal before the re-driver. V Operating Range: 1.8V 0.1V DD Whereas the integrated de-emphasis circuitry provides exibility Packaging (Pb-free & Green): with signal integrity of the PCI-express signal after the Re- 36-pad TQFN (ZF36) Driver. A low-level input signal detection and output squelch function is provided for both channels. Each channel operates fully independantly. When a channel is enabled (EN x=1) and operating, that channel s input signal level (on xl+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to VDD via a high impedance resistor. In addition to providing signal re-conditioning, Pericoms PI2EQX4401D also provides power management Stand-by mode operated by a Bus Enable pin. A differential clock buffer is provided for test and other system requirements. This clock function is not used by the data channels. 08-0241 PS8872H 09/26/08 1OUT- OUT+ SEL3 B SEL2 B SEL1 B SEL0 B CLK IN- CLK IN+ PI2EQX4401D 2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer with Clock Buffer & Signal Defect FeaTure Pin Description Block Diagram 36 35 34 33 32 31 30 29 LVCMOS SIG x V DD 1 28 V DD AI+ 2 27 A + 0 CML AI- 3 26 CML A - 0 xO+ xl+ GND 4 25 GND Limiting Equalizer AV 5 24 Amp DD AGND GND xl+ xO- 6 23 V DD V DD B + 7 22 SEL 0:1 0 BI+ B - 8 21 0 BI- SEL 2 x SEL 9 20 GND GND V 10 19 DD IREF 11 12 13 14 15 16 17 18 CLKIN- OUT0- Buffer CLKIN+ OUT0+ CLK IREF 08-0241 PS8872H 09/26/08 2 SIG A SIG B SEL0 A SEL1 A SEL2 A SEL3 A EN A EN B