A product Line of Pb Diodes Incorporated Lead-free Green PI3DPX1203B DisplayPort 1.4 HBR3 Linear Redriver with Latency-Free, DP Transparent Link Training support Description Applications PI3DPX1203B is the DisplayPort 1.4 compliant, up to 4 channel, Notebook, Desktop, AIO PC 8.1 Gbps HBR3 Linear Redriver with Link Training transparency Display Monitors support. Displayport source-side and sink-side devices commu- Active Adaptors, Dongles, Docking nicate through the AUX transaction between the source and the sink-side devices. Input Equalization, Voltage Swing and Flat Gain control can be configured with pin-strapping or I2C programing to optimized Main Link high speed signals over a variety of physical medium by reducing inter-symbol interference. Pericom s Linear Redriver AC-coupled Transmier DP Mainlink Chipset DP++ CPU PI3DPX1203B Tx technology can deliver 2 times better additive jitters performance dGPU Linear ReDriver than traditional Redrivers. Aux P/N Linear Equalizer always provide very flexible component place- ment, cascade connection and easy adjustment aer tft he Redriver location changes during the product development events. Figure 1-1 DP1.4 HBR3 Redriver in the NB PC Features Ordering Information Compliant with VESA DisplayPort 1.4 specicfi ation up to 8.1 Gbps Link Rate Package Ordering Number Code Package Description Latency-free for the variable video frame rate support Dual mode DisplayPort support 32-pin, Very Thin Quad Flat PI3DPX1203BZLEX ZL Linear Redriver allows flexible placement with DP Main Link No-Lead (TQFN) (3X6mm) boost setting 42-pin, Very Thin Quad Flat PI3DPX1203BZHEX ZH No-Lead (TQFN) (3.5x9mm) Ideal for DP Alt Type-C Source and Sink-side application with PD Controllers with Aux Link Training Transparent Industrial Temperature, 42-pin, Mode support PI3DPX1203BZHIEX ZH Very Thin Quad Flat No-Lead (TQFN) (3.5x9mm) Linear Equalizer increases Link Margin with Sink-side DFE Notes: (Decision Feedback Equalizer) 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU Independent Main Link channel configuration for 4-bit (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See A product Line of Diodes Incorporated PI3DPX1203B 2. General Information 2.1 Revision History Revision Description of Changes Ch2. 32-pin TQFN package added. Improve EQ , Stand-by power consumption from PI3DPX1203 DP1.4 Linear Oct 2016 Redriver. Support I2C slave programming mode. Feb 2017 Ch5. DP1.4 CTS compliance test report added Ch2. ZH42 pin-out typo fixed. Pin6, 12, 30 changed to NC. Mar 2017 Ch4. No index Byte support Ch5. Gp, GF-gain, V1dB 4G typical value updated Ch5. power consumption IDDQ = typ 0.2uA, max 1mA IDD = typ 243mA, max =290mA. May 2017 Ch5. Power-up timing diagram, PRSNT application schematics added Jun 2017 In 42-pin package, clarified NC and DNC pins Jul 2017 Application reference schematic updated to support HPD IRQ Dec 2017 Package marking added (p42). Ordering Information Deleted Section 2.3 Related Products Features Jul 2018 Section 4.4 Output -14dB Compressing Setting Section 4.5 EQ Setting Section 6.4 AX/DC Characteristics Figure 6-6 Peaking Gain Definition Sept 2019 Part Marking 2.2 Similar Products Comparison PI3DPX1203B PI3DPX1203 Key Features New silicon. Improved IDDQ = 0.2mA and IDD Old version. IDDQ = 2mA typ together. Optimized setting for the DP 1.4 speed. Package Pin-out Drop in compatible with PI3DPX1203 version PI3DPX1203B www.diodes.com September 2019 2 of 45 Document number DS39880 Rev 2-2 Diodes Incorporated