A product Line of Pb Diodes Incorporated Lead-free Green PI3EQX25904 25Gbps 4-Channel ReDriver with Linear Equalization Features Description 2.5 to 25Gbps Serial Link with Linear Equalizer D io d e s PI 3E QX 259 0 4 i s a mu lt i- d at a r at e , fou r d i fferent i a l c h a n ne l s R eD r i ver. e Th d e v ic e prov id e s prog r a m m a ble l i ne a r Supports SAS3/ SAS4/ IB FDR/ PCIe4/ UPI Protocols equalization, output swing, and flat gain by either pin strapping Supporting Four Differential Channels 2 option or I C control to optimize performance over a variety of Handles up to 20dB Channel Loss physical mediums by reducing intersymbol interference. (~30 FR4 Trace or 7m of High-Speed Low-Loss Cable) Independent Channel Configuration of Receiver PI3EQX25904 supports four 100 d ifferential CML data I/Os Equalization, Output Swing, and Flat Gain and extends the signals across other distant data pathways on the Rate and Coding Agnostic users platform. Transparent to Link Training, OOB 2 e iTh ntegrated equalization circuitry provides flexibility with Pin Strap and I C Selectable Device Programming signal integrity of the signal before the ReDriver, whereas the 2 3-bit Selectable Address bit for I C integrated linear amplifier/buffer circuitry provides flexibility Supply Voltage: 3.3V0.3V with signal integrity of the signal after the ReDriver. Industrial Temperature Range: -40C to 85C 2 Pin Strap Value Latched into I C Register Applications Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Networking Enterprise Halogen and Antimony Free. Green Device (Note 3) Server Packaging (Pb-free & Green): Storage 42-Contact TQFN (9mm 3.5mm) Pin Configuration (Top-Side View) Block Diagram Conditional Input threshold pullup, 50-Ohm, Detection 4K-Ohm or HIZ 39 42 41 40 EQ2 1 38 FG1 VCC SW1 2 37 FG0 VCC 3 36 VCC CML Input buffer A0RX+ 4 35 A0TX+ A0RX- 5 34 A0TX- O+ I+ Linear Equalizer Buffer VCC 6 VCC 33 Amp I- O- 7 A1RX+ A1TX+ 32 A1RX- 8 A1TX- CML output 31 Conditional input amplifier VCC 9 30 VCC Load: 50-Ohm or Equalization 78K-ohm A2RX+ 10 control (3-bits) 29 A2TX+ VCC Flat Swing A2RX- 11 28 A2TX- gain control control VCC 12 27 VCC A3RX+ 13 26 A3TX+ Flat gain Output Swing control (2-bits) A3RX- control (2-bits) 14 25 A3TX- Power PRSNT VCC 15 24 VCC management I2C RESET 16 23 RXDET Repeats 4x AD1 17 22 I2C DONE 18 19 20 21 Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See A product Line of Diodes Incorporated PI3EQX25904 Pin Description Pin Pin Name Type Description Data Signals 4 A0RX+ I CML inputs for Channel A0 with internal 50 pullup and ~78K to Vbias Rx otherwise. 5 A0RX- I 35 A0TX+ O CML outputs for Channel A0 with internal 50 pullup, 4K to Vbias Tx, or high impedance. 34 A0TX- O 7 A1RX+ I CML inputs for Channel A1 with internal 50 pullup and ~78K to Vbias Rx otherwise. 8 A1RX- I 32 A1TX+ O CML outputs for Channel A1 with internal 50 pullup, 4K to Vbias Tx, or high impedance. 31 A1TX- O 10 A2RX+ I CML inputs for Channel A2 with internal 50 pullup and ~78K to Vbias Rx otherwise. 11 A2RX- I 29 A2TX+ O CML outputs for Channel A2 with internal 50 pullup, 4K to Vbias Tx, or high impedance. 28 A2TX- O 13 A3RX+ I CML inputs for Channel A3 with internal 50 pullup and ~78K to Vbias Rx otherwise. 14 A3RX- I 26 A3TX+ O CML outputs for Channel A3 with internal 50 pullup, 4K to Vbias Tx, or high impedance. 25 A3TX- O Control Signals 2 19 SCL I/O I C SCL Clock. In Master mode (ENI2C floating), SCL is an output. Otherwise, it is an input. 2 18 SDA I/O I C SDA data input/output. 2 42, 41, 17 AD 3:1 I I C programmable address bits with internal 300k pullup. 2 This pin is active in both PIN mode (ENI2C=LOW) and I C mode (ENI2C=HIGH). Cable present detect input. This pin has internal 300K pullup. When HIGH, a cable is not 20 PRSNT I present, and the device is put in lower power mode. When LOW, the device is enabled and in normal operation. When LOW, each channel is programmed by the external pin voltage. When HIGH, each 2 21 ENI2C I channel is programmed by the data stored in the I C bus. When floating, Master mode (Read External EEPROM). Input with 150K pullup and down. Inputs with internal 300k pullup. This pin set the amount of Equalizer Boost in all 1, 40, 39 EQ 2:0 I channels when ENI2C is LOW. Inputs with internal 300k pullup. This pin sets the output Voltage Level in all channels when 2 SW1 I ENI2C is LOW. Inputs with internal 300K pullup resistor. Sets the output flat gain level on all channels 38, 37 FG 1:0 I when ENI2C is low. 2 Inputs with internal 300K pullup resistor. Reset pin for I C. When set low will reset the 16 I2C RESET I registers to default state. www.diodes.com June 2019 PI3EQX25904 Diodes Incorporated Document Number DS41088 Rev 4-2 2