PI3EQX7841 5.0Gbps, 1-port, USB3.0 ReDriver 2 with I C Programming Interface Features Description USB 3.0 compatible 1.2V Pericom Semiconductors PI3EQX7841 is a low power, high Operation performance 5.0 Gbps signal ReDriver designed specifi - Two 5.0Gbps differential signal pairs cally for the USB 3.0 protocol. The device provides program - Adjustable Receiver Equalization mable equalization, De-Emphasis, and Output Swings to op- 2019181716 100 Differential CML I/Os AI+ 1 15 AO+ timize performance over a variety of physical mediums by Pin Configured OAI-utput E2 mphasis and Swing Control 14 AO- reducing Inter-Symbol Interference. PI3EQX7841 supports two 3 EN A 13 EN B Input signal level detect and squelch for each channel GND 100 Differential CML data I/Os between the Protocol ASIC to a 4 12 BI- BO- Automatic Receiver Detect switch fabric, over cable, or to extend the signals across other dis- 5 11 BO+ BI+ 6 7 8 9 10 Low Power : ~330mW tant data pathways on the users platform. The integrated equal - ization circuitry provides flexibility with signal integrity of the Industrial Temp Support -40C~ +85C signal before the ReDriver. A low-level input signal detection and AutoSlumbe mode for adaptive power management output squelch function is provided for each channel. Stand-by Mode Power Down State Single Supply Voltage: 3.3V10% When the channels are enabled, EN = 0, and operating, that chan- Packaging: 20-Pin TQFN (4x4mm) nels input signal level (on xI+/-) determines whether the output is active. If the input signal level of the channel falls below the active Pin Diagram (Top Side View) threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to signal conditioning, when EN = 1, the device enters a low power standby mode. The PI3EQX7841 also 3.3V 2 includes a fully programmable I C interface. When I2C control Operation mode is enabled, I2C EN = 1, equalization, output swing, and de-emphasis settings can be adjusted by programming the re- 2019181716 AI+ 1 lated registers. 15 AO+ AI- 2 14 AO- 3 EN 13 I2C EN GND 4 12 BI- BO- 5 11 BO+ BI+ 6 7 8 9 10 Figure1 External USB 3.0 Storage Device ReDriver Block Diagram Signal Detection USB 3.0 Cable CML CML XO+ XI+ Limiting Equalizer Amp XI XO EQ x - Repeated 2 times - Power Management www.pericom.com P-0.1 02/22/13 13-0021 1 PI3EQX6701PI3EQX7711 VDD33 DNC VDD12 VDD12 EQ B OS A SCL EQ B RxDet DE B DE B / A0 DE A / SDA DE A EQ A EQ A OS B / A1 RES VDD33 DNC VDD12 VDD12PI3EQX7841 2 5.0Gbps, 1-Port, USB3.0 ReDriverwith I C Programming Interface Pin Description Pin Pin Name Type Description 1 AI+ 2 AI- CML input channels. With Selectable input termination between 50 to internal V or bias Input 11 BI+ 60k to GND. 12 BI- Chip Enable. When the pin is drivenLo, chip is in normal operation. When the pin is 3 EN Input driven High, chip is in power down mode. With internal 200k pull-down resistor. 4 BO- 5 BO+ Selectable output termination between 50 to internal V , 2k to internal V , or bias bias Output 14 AO- Hi-Z. 15 AO+ 6 DNC / DNC Do Not Connect 16 DNC Set the equalization of two channels. These are Tri-level input pins. When set toHIG 7 EQ B, Input the pin becomes Logic1 when set toope, the pin becomesope, when set to 17 EQ A lo, the pin becomes logic0 . Please refer to Mode Adjustment on page 3. Set the de-emphasis of the output CML buffer for Channel B. This is a Tri-level input pins When set tohig, the pin becomes logic1 when set toope, the pin becomes ope when set tolo, the pin becomes logic0 . Please refer to Mode Adjustment on 8 DE B / A0 Input page 3. 2 2 This pin is also used for I C programming interface. When set tohig or floating, I C 2 address bit A0 is set to1 . When set tolo, I C address bit A0 is set to0 . Set the output swing of Channel B. This is a Tri-level input pins When set toHIG, the pin becomes Logic1 when set toope, the pin becomesope, when set tolo, the pin becomes logic0 . 9 OS B / A1 Input 2 2 This pin is also used for I C programming interface. When set tohig or floating, I C 2 address bit A1 is set to1 . When set tolo, I C address bit A1 is set to0 . 10 VDD33 Power 3.3V Voltage Supply 20 2 2 I C Control Enable. When the pin is driven High, chip is in I C Control Mode. When 13 I2C EN Input the pin is driven Low, chip is in pin strap control mode. With internal 200k pull-down resistor. Set the de-emphasis of the output CML buffer for Channel A. These is a Tri-level input pin. When set tohig, the pin becomes logic1 when set toope, the pin becomes DE A / Input/ope when set tolo, the pin becomes logic0 . Please refer to Mode Adjustment on 18 SDA Output page 3. 2 This pin is also used as Data Line for I C programming interface. Set the output swing of Channel A. This is a Tri-level input pins When set toHIG, the pin becomes Logic1 when set toope, the pin becomesope, when set tolo, OS A / 19 Input the pin becomes logic0 . SCL 2 This pin is also used as Clock Line for I C programming interface. Center Pad GND GND Supply Ground. www.pericom.com P-0.1 02/22/13 13-0021 2