ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI ReDriver with 2 Optimized Equalization & I C Buffer Features Description Pericom Semiconductors PI3HDMI101 1:1 active ReDriver Supply voltage, V = 3.3V 5% DD circuit is targeted for high-resolution video networks that are TM Support for both DVI and HDMI signals TM based on DVI/HDMI standards and TMDS signal processing. Supports both AC-coupled and DC-coupled inputs The PI3HDMI101 is an active ReDriver with Hi-Z outputs. TM Supports Deep Color The device receives differential signals from selected video High Performance, up to 2.5 Gbps per channel components and drives the video display unit. This solution also 2 provides a unique advanced pre-emphasis technique to increase 5V Tolerance on I C path rise and fall times which are reduced during transmission across Integrated 50-Ohm (10%) termination resistors at each high long distances. speed signal input Each complete HDMI/DVI channel also has slower speed, side Rx Sense Support, CLK-off channel is switched to 250K-Ohm band signals, that are required to be switched. Pericoms solution pull-up vs. 50-Ohm pull-up provides a complete solution by integrating the side band buffer Con gurable output swing control together with the high speed buffer in a single solution. Using (400mV, 500mV, 600mV, 750mV, 1000mV) Equalization at the input of each of the high speed channels, Con gurable Pre-Emphasis levels Pericom can successfully eliminate deterministic jitter caused by (0dB, 1.5dB, 3.5dB, & 6.0dB, 9.0dB) long cables from the source to the sink. The elimination of the Con gurable De-Emphasis deterministic jitter allows the user to use much longer cables (up (0dB, -3.5dB, -6.0dB, -9.5dB) to 25 meters). Optimized Equalization The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 36- Single default setting will support all cable lengths bit Deep Color support, which is offered by HDMI revision 8kV Contact ESD protection on all input/output data channels 1.3. The PI3HDMI101 also provides enhanced robust ESD/EOS per IEC 61000-4-2 protection of 8kV, which is required by many consumer video networks today. Hot insertion support on output high speed pins & SCL/SDA pins only The Optimized Equalization provides the user a single optimal setting that can provide HDMI compliance for all cable lengths: Propagation delay 1ns 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. High Impedance Outputs when disabled Pericom also offers the ability to ne tune the equalization settings Packaging (Pb-free & Green): 42-contact TQFN (ZH42) in situations where cable length is known. For example, if 25meter cable length is required, Pericom s solution can be adjusted to 16dB EQ to accept 25meter cable length. PS8924C 10/05/09 09-0055 1 All trademarks are property of their respective owners.ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 TM 1:1 Active HDMI Redriver with 2 Optimized Equalization & I C Buffer Pin Con guration 42414039 SCL T 1 38 EQ S0 VDD 2 37 EQ S1 36 GND GND 3 OUT CLK IN CLK 4 35 OUT CLK+ IN CLK+ 5 34 VDD 6 33 VDD OUT D0 7 32 IN D0 31 OUT D0+ IN D0+ 8 GND GND 9 GND 30 OUT D1 10 29 IN D1 OUT D1+ 11 28 IN D1+ 12 27 VDD VDD 26 OUT D2 IN D2 13 OUT D2+ IN D2+ 14 25 GND 15 24 GND VDD 16 23 Rx Sense 17 22 OC S3 DCC EN 18192021 TMDS Receiver Block Each high speed data and clock input has the same integrated equalization that can eliminate deterministic jitter caused by input traces or cables. All activity can be con gured using pin strapping. The Rx block is designed to receive all relevant signals directly from the HDMI connector without any additional circuitry, 3 High speed TMDS data, 1 pixel clock, and DDC signals. Pixel clock channel has following termination scheme for Rx Sense support. AV DD Rx Sense LR switch is open, CLK+/- 2 termination is 250k R 2 HR switch is closed, CLK+/- 2 250K ohm termination is 50 Control Although the TMDS clock input channel (pin Rx Sense 4 and 5) has different termination scheme when port is off, user can still connect TMDS data channels to these pins for better layout if R 1 required. Any of the 4 differential inputs and outputs can have data or clock signals passing CLK+/- through. PS8924C 10/05/09 2 09-0055 All trademarks are property of their respective owners. OE IADJ OC S0 SCL R OC S1 SDA R OC S2 SDA T