PI3HDMI1310-A HDMI Switch with non-blocking EQ Circuitry Features Description Pericom Semiconductor s PI3HDMI series of switch circuits Differential channel 3:1 Mux/DeMux for TDMS signals are targeted for high-resolution video networks that are based on 3:1 Mux/DeMux for DDC signals DVI/HDMI standards. The PI3HDMI1310-A is a 3-to-1 HDMI non-EQ blocking circuitry to utilize ideal EQ found in Mux/DeMux Switch. It is designed for low bit-to-bit skew and main receiver chipset high channel-to-channel noise isolation. The maximum DVI/ Low power consumption to support Energy Star HDMI data rate of 3.4Gbps provides the resolution required Compliance by next generation HDTV and PC graphics. Three differential Data rate support up to 3.4Gbps (16bit color depth per channels are used for data (video signals for DVI or audio/video channel) signals for HDMI), and one differential channel is used for Clock for decoding the TMDS signals at the outputs. 2 pin control for port selection 3.3V power and 5V standby power PI3HDMI1310-A was designed specifically to meet ATC-Sink ESD protection on all I/O pins requirement for the HPD ports. The high speed video ports and DDC ports can be either source or sink. 8kV contact per IEC61000-4-2 7kV HBM per JESD22 Packaging (Pb-free & Green): 72 - Contact TQFN All TMDS I/O pins are protected with Pericom s ESD protection circuits, supporting protection against ESD damage as high as 8kV contact per IEC6000-4-2 spec. Block Diagram Pin Configuration (Top View) 4 - differential D0-D3A TMDS Lanes 4 - differential 72 71 70 69 68 67 66 65 64 63 4 - differential GND 1 62 GND D0-D3B D0-D3 VDD TMDS Lanes TMDS Lanes D2-A 2 61 4 - differential D2+A 3 60 HPD Sink D0-D3C TMDS Lanes D3-A 4 59 SEL2 D3+A 5 58 SEL1 VDD 6 57 OE D0-B VDD DDC CLK A 7 56 D0+B 8 55 D0- DDC DATA A D1-B 9 54 D0+ DDC CLK B DDC CLK D1+B 10 53 GND DDC DATA DDC DATA B D2-B 11 52 D1- DDC CLK C 12 51 D1+ D2+B DDC DATA C 13 50 VDD VDD D3-B 14 49 D2- D3+B 15 48 D2+ GND 16 47 GND HPD A D0-C 17 46 D3- D0+C 18 45 D3+ HPD B HPD Sink D1-C 19 44 VDD D1+C 20 43 DDC Data HPD C 100k VDD DDC CLK 21 42 22 41 GND D2-C GND 23 40 D2+C 24 39 GND D3-C 25 38 GND D3+C Control Logic GND 26 37 27 28 29 30 31 32 33 34 35 36 GND SEL1 SEL2 OE 12-0196 1 www.pericom.com 01/25/13 GND GND DDC DataA D1+A DDC CLKA D1-A GND D0+A DDC DataB D0-A DDC CLKB HPDC HPDB VDD50 DDC DataC HPDA DDC CLKC VDD50 GND GNDPI3HDMI1310-A HDMI Switch with non-blocking EQ Circuitry Pin Description Pin Pin Name Pin Type Description 69, 68, 71, 70, DxA (X = 0, 1, 2, 3) I/O Port A High Speed inputs 3, 2, 5, 4, 8, 7, 10, 9, 12, DxB (X = 0, 1, 2, 3) I/O Port B High Speed inputs 11, 15, 14 18, 17, 20, 19, DxC (X = 0, 1, 2, 3) I/O Port C High Speed inputs 23, 22, 25, 24 HPD open-drain outputs for each port. Logic will follow truth table on page 7. 65, 66, 67 HPDA, HPDB, HPDC Output External 1Kohm pull-up to 5V is required 5.0V voltage rail from HDMI/DVI connector. Used during 33, 64 VDD50 Power standby-mode. 60 HPD Sink Input GP I/O pin from SCALAR. Internal 100Kohm pull-down. 29, 28, 32, 31, 2 DDC CLKx, DDC Datax I/O I C signals for DDC communication on TMDS ports 35, 34, 42, 43 55, 54, 53, 52, 51, 49, 48, 46, DX (x = 0, 1, 2, 3) I/O 4-differential high speed Output signals 45 Selection for D0-D3 and DDC signals (Select Pins, see truth 58, 59 SEL1, SEL2 Inputs tables on page 5) 6, 13, 21, 44, V Power 3.3V Power Supply DD 50, 56, 61 1, 16, 26, 27, 30, 36, 37, 38, GND Power Ground. 39, 40, 41, 53, 62, 63, 72 Output enable (Active LOW). When HIGH, all outputs are 57 OE Input Hi-Z and chip is placed into Standby Mode. Under Standby Mode, the current supply is from VDD50. www.pericom.com 01/25/13 12-0196 2