ARC OUT SCL SINK EQ S0 SDA SINK OC S0 HPD SINK SEL1 ROUT S0 OEB SCL1 HPD2 SDA1 SDA2 HPD1 GND SCL2 CLKN2 D2P1 CLNP2 D2N1 D1P1 D0N2 D0P2 D1N1 COMPANY CONFIDENTIAL PI3HDX621 3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching Features Description yyHDMI 1.4b compliant for sink side application PI3HDX621 is the active-type 2:1 switch compliant to HDMI 1.4b specicfi ation, featuring equalized TMDS input and pre- yyOperation up to 3.4 Gbps per lane emphasized TMDS outputs, with 3.4 Gbps high speed and yySupport up to 48-bit per pixel Deep Color long cable application. yyFast switching between two TMDS input ports Two TMDS input ports switch fast in the built-in high speed yyProgrammable equalizer, emphasis and amplitude Mux through port selection pins. Redriver boost the input settings to achieve optimized TMDS signal integrity signal quality, adjust known channel losses at the transmit- ter and restore signal integrity at the receiver. It offers doube yyEach input can be AC coupled or DC coupled, while termination or open drain output mode by output selection the output will maintain TMDS compliance DC pin. coupled, current steering signals TMDS output can shut down to reduce power dissipation yyIdle clock detection function for output squelch and by sink side HPD detection status. DDC 2:1 Mux and ARC auto standby drivers are integrated. PI3HDX621 is specified to operate yyIntegrated ARC(Audio Return Channel) and DDC over -40 to 85 C temperature range with 8kV ESD protec- Mux tion pins. yyIntegrated ESD protection on I/O pins to connector yy3.3V single power supply yy8 KV contact per IEC61000-4-2, level 4, 8 KV HBM yyIndustrial temperature coverage yyPackaging (Pb-free & Green): 48-contact LQFP (FB48) Pin Configuration Application yyNotebook Computers, Set Top Box yyA/V Home Entertainment Systems 48 47 46 45 44 43 42 41 40 39 38 37 yyDongle and Switches 1 CLKN VDD 36 2 D1N2 35 CLKP 3 D1P2 34 GND GND 4 33 D0N D2N2 5 32 D0P Typical Application Block Diagram D2P2 6 31 VDD PI3HDX621 CLKN1 7 LQFP- 48 VDD REG 30 Source CLKP1 8 29 D1N EQ Device:A GND 9 28 D1P D0N1 10 27 D2N D0P1 11 26 D2P Sink VDD 12 25 Driver SPDIF IN Device 13 14 15 16 17 18 19 20 21 22 23 24 Signal EQ Device:B PI3HDX621 All trademarks are property of their respective owners. www.pericom.com 10/28/14 1 14-0144PI3HDX621 3.4Gbps HDMI1.4b Active 2:1 Switch with ARC and Fast Switching Functional Block Diagram VDD REG HPD 1:2 VDD LDO (1) HPD SINK 120K VDD HPD Detector R T R T VDD CLKP1/N1 D 0:2 P1/N1 ROUT 2:1 ROUT CLKP/N Active Mux D 0:2 P/N R T R T CLKP2/N2 D 0:2 P2/N2 OEB ROUT S0 Control Logic OC S0 SEL1 EQ S0 SCL1 SCL SINK SDA1 2:1 Mux SDA SINK SCL2 SDA2 S PDIF IN ARC OUT Note: (1) If HPD SINK input voltage is higher than 5V, serial resister is recommended. The resister value is about 20 -25k. All trademarks are property of their respective owners. www.pericom.com 10/28/14 2 14-0144