PI3V713-A 3.3V, 7-Channel Analog Video Switch Features Description Designed specifically to switch VGA signals Pericoms PI3V713-A is a 7-channel video mux/demux used to switch between multiple VGA sources or end points. In a 7-Channels for VGA signals (R,G,B, Hsync, Vsync, DDC notebook application where analog video signals are found in both Data, and DDC CLK) the notebook and the dock, a switch solution is required to switch V = 3.3V +/-10% DD between the two video port locations. With the high bandwidth DDC path will operate as a 5V to 3.3V level shifter of ~1.7GHz, the signal integrity will remain strong even through H/V output buffer with +/-24mA drive the long FR4 trace between the notebook and the docking station. ESD tolerance on video I/O pins is up to 12kV HBM per In addition to high signal performance, the video signals are also JEDEC standard protected against high ESD with integrated diodes to V and DD -3dB BW of 1.7GHz (typ) GND that will support up to12kV HBM ESD protection. Low Xtalk, (-38dB typ) Application Low and Flat ON-STATE resistance (R = 4.8-Ohm, on Routing VGA signals with low signal attenuation and high ESD. R (Flat) = 0.5ohm, typ) on Low input/output capacitance (Con = 5.6pF, typ) Packaging (Pb-free and Green): 32-contact TQFN (ZLE) Applications Routes physical layer signals for high bandwidth digital video Block Diagram Pin Diagram R R1 G G1 B B1 32 31 30 29 28 R2 1 27 R R1 G2 2 26 B2 G R2 3 25 GND G1 +5V 4 24 G2 VDD H SOURCE H1 OUT 5 23 VDD Dual B Buffer V SOURCE V1 OUT 6 GND 22 B1 H SOURCE 7 21 V SOURCE B2 8 20 Reserved H1 OUT H2 OUT 9 19 Dual SDA SOURCE H2 OUT Buffer V2 OUT 10 SCL SOURCE 18 V1 OUT GND 11 17 V2 OUT Control SEL 12 13 14 15 16 Logic SDA1 SDA SOURCE SCL1 5V to 3.3V Level Shifter SCL SOURCE SDA2 SCL2 10-0192 PS9101 06/29/10 1 SDA1 VDD SDA2 GND SCL1 SEL SCL2 TEST 5V VDD GNDPI3V713-A 3.3V, 7-Channel Analog Video Switch Pin Description Pin Number Pin Name Pin Type Description 1 R I/O Red signal from VGA Transmitter 2 G I/O Green signal from VGA Transmitter 3 GND Ground Ground 4 V Power 3.3V +/-10% power rail DD 5 B I/O Blue signal from VGA Transmitter 6 H SOURCE I Horizontal Synchronous signal from VGA Transmitter 7 V SOURCE I Vertical Synchronous signal from VGA Transmitter 8 Reserved I For normal operation, this pin needs to be tied HIGH 9 SDA SOURCE I/O DDC, data signal from VGA Transmitter 10 SCL SOURCE I/O DDC, clock signal from VGA Transmitter 11 GND Ground Ground 12 SDA1 I/O DDC, data signal for VGA output port 1 13 SDA2 I/O DDC, data signal for VGA output port 2 14 SCL1 I/O DDC, clock signal for VGA output port 1 15 SCL2 I/O DDC, clock signal for VGA output port 2 16 5V V Power 5V +/-10% Power rail DD 17 V2 OUT O Vertical Synchronous buffered signal for VGA output port 2 18 V1 OUT O Vertical Synchronous buffered signal for VGA output port 1 19 H2 OUT O Horizontal Synchronous buffered signal for VGA output port 2 20 H1 OUT O Horizontal Synchronous buffered signal for VGA output port 1 21 B2 I/O Blue signal for VGA port 2 22 B1 I/O Blue signal for VGA port 1 23 V Power 3.3V +/-10% power rail DD 24 G2 I/O Green signal for VGA port 2 25 G1 I/O Green signal for VGA port 1 26 R2 I/O Red signal for VGA port 2 27 R1 I/O Red signal for VGA port 1 28 GND Ground Ground Description is TEST pin to enable TEST mode. IF this pin is LOW, then test 29 TEST Input mode is enabled. For normal usage disable TEST mode by holding this pin high, or floating. There is an internal 100Kohm pull-up on this pin Control signal. 30 SEL I If pin 30 is LOW, port 1 is chosen If pin 30 is HIGH, port 2 is chosen 31 GND Ground Ground 32 VDD Power 3.3V +/-10% power rail PS9101 06/29/10 10-0192 2