PI3V724 1 to 2 VGA Demux Features Description Full VGA 1:2 demux with VSIS compliance Pericoms PI3V724 is a 7-channel video mux/demux used to switch between multiple VGA sources or end points. In a note- R, G, B, Hsync, Vsync, DDC data, and DDC clk book application where analog video signals are found in both channels are switched the notebook and the dock, a switch solution is required to switch Integrated monitor detection circuit allows Automatic or between the two video port locations. With the high bandwidth manual control of ~1.7GHz, the signal integrity will remain strong even through Generates hot plug output signal to inform system when the long FR4 trace between the notebook and the docking sta- monitor is present or not tion. In addition to high signal performance, the video signals are Dual Power Supply, 3.3V and 5V also protected against high ESD with integrated diodes to VDD and GND that will support up to +/-4kV contact ESD protection. Integrated DDC level shifter from 5V to 3.3V(bi-directional) Integrated 5V H/V output buffer with +/-24mA drive In addition to switching, the product also integrates a monitor ESD tolerance on video I/O pins up to +/-4kV contact per detection feature. The monitor detection feature works indepen - IEC61000-4-2 specicfi ation dently on each of the two outputs and allows automatic switching -3dB BW of 1.7GHz (typ) as well as a self generated HPD signal that lets the system know Low Xtalk, (-38dB typ) when a monitor is connected or disconnected. Low and Flat ON-STATE resistance (Ron = 4-Ohm, Ron(Flat) = 0.5ohm, typ) Low input/output capacitance (Con = 5.6pF, typ) Packaging (Pb-free and Green): Pin Diagram 32-contact TQFN (ZL) 32 31 30 29 28 1 R 27 R1 2 26 G R2 3 25 GND G1 4 24 G2 VDD 5 23 VDD B 6 GND 22 B1 H SOURCE 7 21 V SOURCE B2 8 20 MS H1 OUT 9 19 SDA SOURCE H2 OUT SCL SOURCE 10 18 V1 OUT Rref 11 17 V2 OUT 12 13 14 15 16 www.pericom.com 10/22/14 14-0168 1 SDA1 Test SDA2 GND SCL1 Priority/SEL SCL2 OUT VDD5 IN CEV V V V V V V V PI3V724 1 to 2 VGA Demux Block Diagram Result detect EN B1 Result B detect V EN V B2 V V MS Logic OUT Priority/SEL Control CE Timer Rref pulse Detection Start Logic +5V To timer V1 Buffer V SOURCE Buffer V2 G G1 R R1 G2 R2 +5V H SOURCE H1 OUT Buffer Buffer H2 OUT Control Logic SDA1 SDA SOURCE SCL1 5V to 3.3V Level Shifter SCL SOURCE SDA2 SCL2 www.pericom.com 10/22/14 14-0168 2 V V V