PI3VDP12412 4-Lane DisplayPort Rev 1.2 Compliant Switch Features Description 4-lane, 1:2 mux/demux that will support RBR, HBR1, or Pericom Semiconductors PI3VDP12412 mux/demux is targeted HBR2 for next generation digital video signals. This device can be used to connect a DisplayPort Source to two Independent Display- 1-channel 1:2 mux/demux for DP HPD signal Port Sinks or to connect two DisplayPort sources to a single DP 1-differential channel 1:2 mux/demux for DP Aux signal display. with support up to 720Mbps PI3VDP12412 supports DisplayPort 1.2 which requires a data -1.6dB Insertion Loss for Dx channels 2.7 GHz (TQFN) rate of 5.4 Gbps. PI3VDP12412 offers excellent signal integrity at -3dB Bandwidth for Dx channels: 4.6GHz (TQFN) this high data rate with very low insertion loss, good return loss, Return loss for Dx channels 2.7GHz: -16dB (TQFN) and very small crosstalk. Low Bit-to-Bit Skew , 5ps typ (between + and - bits) PI3VDP12412 is available in two package types, a 5 mm x 5 mm 48 BGA and a 3.5 mm x 9 mm 42 TQFN. The BGA consumes less Low Crosstalk for high speed channels: -28dB 5.4 Gbps board space. The TQFN achieves slightly better signal integrity. Low Off Isolation for high speed channels: -22dB 5.4 Gbps V Operating Range: 3.3V +/-10% DD ESD Tolerance: 2kV HBM Application Low channel-to-channel skew, 35ps max Routing of DisplayPort signals with low signal attenuation be- tween source and sink. Packaging (Pb-free & Green): 42 TQFN (ZHE) 48 BGA (NEE) Block Diagram D0+ D0+A D0- D0-A D1+ D1+A - D1 D1-A D2+ D2+A D2- D2-A D3+ D3+A D3- D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B AUX+ AUX+ A AUX- AUX-A HPD HPD A AUX+ B AUX- B HPD B SCL A (BGA package only) SDA A (BGA package only) SCL B (BGA package only) SDA B (BGA package only) GPU SEL DDC AUX SEL (BGA package only) Logic Control AUX HPD SEL (TQFN package only) OE 12/17/12 12-0293 1PI3VDP12412 4-Lane DisplayPort Rev 1.2 Compliant Switch Pin Assignment (TQFN-42, ZHE) Truth Table for 42 pin package AUX GPU HPD OE SEL SEL Function High Low Low Port A active for all channels GND 1 38 D2-A High Low High Port A for HS, port B for HPD/AUX 2 37 D2+A GPU SEL High High Low Port B for HS, port A for HPD/AUX D0- 3 36 D3-A High High High Port B active for all channels 4 35 D0+ D3+A AUX HPD SEL 5 34 Low x x All I/O s are hi-z and IC is power down Vdd D1- 6 33 D0-B D1+ 7 32 D0+B D2- 8 31 D1-B (43) D2+ 9 30 D1+B GND 10 29 D3- D2-B 11 28 D3+ D2+B 12 27 Vdd D3-B 13 26 D3+B AUX- 14 25 AUX+ OE 15 24 HPD B AUX-A 16 23 AUX+A HPD A 17 22 GND GND Pin Assignment (48-Ball BGA, NEE) DDC 5 6 2 3 4 7 8 9 1 GPU AUX GPU OE SEL SEL Function Vdd D3-A A D0-A D1-A D2-A D3+A GPU SEL SEL Port A active for AUX, HPD & HS High Low Low D0+B D0-B B D0- D0+ GND D0+A D1+A D2+A OE channel DDC Port A active for DDC, HPD, & HS AUX GND C High Low High SEL channel D1- D1+ D1+B D1-B D Port B active for AUX, HPD & HS High High Low channel D2- D2+ D2+B D2-B E Port B active for DDC, HPD & HS High High High channel D3+B D3-B D3- D3+ F Low x x all I/Os are hi-z and IC is power down GND GND G SCL B AUX+B SCL A HPD B GND GND AUX+A AUX- AUX+ H SDA B SDA A AUX-A AUX-B HPD HPD A Vdd J 12/17/12 12-0293 2 42 D0-A 18 HPD 41 D0+A 19 AUX-B 40 D1- A 20 AUX+B 39 21 D1+ A Vdd