PI3WVR12612 HDMI 2.0, DisplayPort 1.2 Video Switch Features Description 4-lane, 1:2 mux/demux that will support RBR, HBR1, or Pericom Semiconductors PI3WVR12612 is a multi-standard HBR2 video switch with wide voltage range capability. It supports DisplayPort 1.2, HDMI 2.0, and emerging and proprietary standards. Data rate: 3.4 Gbps to 6.0 Gbps for high data channels PI3WVR12612 can pass high-speed signals up to 1.2 V peak- 1-channel 1:2 mux/demux for HPD signal to-peak differential with a common-mode voltage from 0 to Differential switch matrix for DP AUX and HDMI DDC 3.4V. The wide voltage range allows DC-coupled multi-standard supports 720 Mbps high-speed DP AUX operation. Eliminating AC coupling capacitors saves board space -1.8 dB Insertion Loss for Dx channels 2.7 GHz and improves signal integrity for dense PCB designs. -3 dB Bandwidth for Dx channels: 4.1 GHz e Th high speed channels can also pass 0V-3.3V CMOS signals up to 1MHz. Return loss for Dx channels 2.7GHz: -14 dB In addition to four high-speed lanes, PI3WVR12612 also switch- Low Crosstalk for high speed channels: -28 dB 5.4 Gbps es AUX, DDC, and HPD signals. Low Off Isolation for high speed channels: -22dB 5.4 Gbps Low channel-to-channel skew, 35ps max Low Bit-to-Bit Skew, 5ps typ (between + and - bits) Application V Operating Range: 3.3V +/-10% Routing of DisplayPort and HDMI signals with low signal at- DD tenuation between source and sink. ESD Tolerance: 2kV HBM Packaging (Pb-free & Green): -50-ball TFBGA (NEE) -52-pin TQFN (ZL52) Block Diagram D0+ D0+A AUX+ AUX+A D0- D0-A AUX+B D1+ D1+A SCL A D1- D1-A SCL B SCL D2+ D2+A D2- D0-A D3+ D3+A D3- D3-A AUX- AUX-A D0+B AUX-B D0-B SDA A D1+B SDA B D1-B SDA D2+B D2-B D3+B HPD HPDA D3-B HPDB DDC AUX SEL Logic Control GPU SEL OE All trademarks are property of their respective owners. www.pericom.com 04/17/15 15-0039 1PI3WVR12612 HDMI 2.0, DisplayPort 1.2 Video Switch Pin Assignment (50-Ball TFBGA, NEE) Pin Assignment (52-Pin TQFN, ZL52) 6 4 5 7 9 1 2 3 8 GPU A VDD D3+A D3-A GPU SEL D0-A D1-A D2-A SEL 52 51 50 49 48 OE 47 V 1 DD D0-B D0- D0+ GND D0+A D1+A D2+A OE D0+B B D2-A GND 46 2 45 D2+A DDC GPU SEL 3 AUX GND C D3-A 44 SEL D0- 4 D3+A 43 D0+ 5 D1- D1+ D1+B D1-B D V DDC AUX SEL 42 6 DD 41 D0-B D1- 7 D2+ D2+B D2-B D2- D0+B E 40 D1+ 8 D1-B 39 D2- 9 D3+B D3-B D3- D3+ D1+B D2+ 38 F 10 37 GND D3- 11 GND GND D2-B 36 D3+ 12 G D2+B 35 GND 13 SCL B AUX+B GND SCL A AUX+A D3-B AUX- AUX+ HPD B GND V 34 14 DD H 33 D3+B AUX- 15 SDA A SDA SDA A AUX-A 32 HPD HPD A SCL Vdd SDA B AUX-B AUX+ 16 J SCL A 31 HPD B 17 GND 30 HPD A 18 29 AUX-A HPD 19 AUX+A 28 SCL 20 GND 27 SDA 21 Truth Table 22 23 24 25 26 Control Switch Function DDC GPU AUX D0- OE SEL SEL D3 AUX HPD DDC High Low Low A AUX A HPD A Hi-Z High High Low B AUX B HPD B Hi-Z High Low High A DDC A HPD A Hi-Z High High High B DDC B HPD B Hi-Z High Low Medium A AUX A HPD A DDC A High High Medium B AUX B HPD B DDC B Low x x Hi-Z Hi-Z Hi-Z Hi-Z Medium level = 1/2 VDD = 1.65V All trademarks are property of their respective owners. www.pericom.com 04/17/15 15-0039 2 SDA B D0-A SCL B D0+A AUX-B D1-A AUX+B D1+A V DD GND