PI6ULS5V9511AUEX Diodes Incorporated

PI6ULS5V9511A Hot Swappable I2C Bus/SMBus Buffer Features Description Bidirectional Buffer for SDA and SCL Lines Increases The PI6ULS5V9511A is a hot-swappable I2C-bus and Fan Out SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Prevents SDA and SCL Corruption During Live Board Control circuitry prevents the backplane from connecting to Insertion and Removal from Backplane the card until a stop command or bus idle occurs on the Isolates Input SDA and SCL Lines From Output backplane without bus contention on the card. Compatible with I2C, I2C Fast Mode, and SMBus Standards (up to 400kHz Operation) When the connection is made, the PI6ULS5V-9511A Built-in Rise-Time Accelerators on all SDA and SCL provides bidirectional buffering, which keeps the backplane and card capacitances isolated. Wide Supply Voltage Range: 2.7V to 5.5V Active HIGH ENABLE Input The PI6ULS5V9511A rise-time accelerator circuitry allows Active HIGH READY Open-Drain Output the use of weaker DC pullup currents while still meeting High-Impedance SDA and SCL pins for VCC = 0V rise-time requirements. The PI6ULS5V9511A incorporates a 1.1V Pre-Charge on all SDA and SCL Lines digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low-current Supporting Clock Stretching and Multiple Master mode when asserted LOW, and an open-drain READY Arbitration/Synchronization output pin, which indicates that the backplane and card ESD Protection Exceeds 4000V HBM per JESD22-A114 sides are connected together (HIGH) or not (LOW). Packages Offered: MSOP-8(U), UDFN-8(ZW), and SOIC-8(W) During insertion, the PI6ULS5V9511A SDA and SCL lines are pre-charged to 1.1V to minimize the current required to Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) charge the parasitic capacitance of the chip. Halogen and Antimony Free. Green Device (Note 3) Pin Description Pin Configuration Pin Name Pin No. Description ENABLE 1 Chip enable. Serial clock output to and from SCLOUT 2 the SCL bus on the card Serial clock input to and from SCLIN 3 the SCL bus on the backplane Ground. Connect this pin to a GND 4 ground plane for best results. Figure 1. Top View of MSOP-8 and SOIC-8 Open-drain output . Goes LOW when SDA/SCL READY 5 channels are disconnected. Goes HIGH when the two sides are connected. Serial data input to and from the SDAIN 6 SDA bus on the backplane. Serial data output to and from SDAOUT 7 the SDA bus on the card. VCC 8 Power supply. Figure 2. Top View of UDFN 2x3-8 Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See PI6ULS5V9511A Block Diagram PI6ULS5V9511A Figure 3: Block Diagram PI6ULS5V9511A www.diodes.com December 2018 Document Number 40558 Rev 3 - 2 Diodes Incorporated 2