PI74ALVCH162268
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12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Description
Product Features
Pericom Semiconductors PI74ALVCH series of logic circuits are
PI74ALVCH162268 is designed for low voltage operation
produced in the Companys advanced 0.5 micron CMOS
V = 2.3V to 3.6V
CC
technology, achieving industry leading speed.
Hysteresis on all inputs
This 12-bit to 24-bit registered bus exchanger is designed for 2.3V
Typical VOLP (Output Ground Bounce)
to 3.6V V operation.
cc
< 0.8V at V = 3.3V, T = 25C
CC A
The PI74ALVCH162268 is used for applications in which data
Typical VOHV (Output VOH Undershoot)
must be transferred from a narrow high-speed bus to a wide, lower
< 2.0V at V = 3.3V, T = 25C
CC A
frequency bus.
B-port outputs have equivalent 26 series resistors,
no external resistors are required. The device provides synchronous data exchange between the two
ports. Data is stored in the internal registers on the low-to-high
Bus Hold retains last active bus state during 3-state
transition of the clock (CLK) input when the appropriate clock
eliminates the need for external pullup resistors
enable (CLKEN) inputs are low. The select (SEL) line is
Industrial operation at 40C to +85C
synchronous with CLK and selects 1B or 2B input data for the A
Packages available: outputs.
56-pin 240 mil wide plastic TSSOP (A56)
For data transfer in the A-to-B direction, a two stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
Logic Block Diagram
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
The B outputs, which are designed to sink up to 12mA, include
equivalent 26 resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to V through a pullup resistor, the minimum value
CC
of the resistor is determined by the current-sinking capability of
the driver. Because OE is being routed through a register, the
active state of the outputs cannot be determined prior to the arrival
of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
06-0138 PS8352A 07/22/05
1PI74ALVCH162268
12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs
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Product Pin Description Product Pin Configuration
Pin Name Description
OE Output Enable Input (Active LOW)
OEA OEB
1 56
CLK Clock
CLKEN1B CLKENA2
2 55
SEL Select (Active Low)
2B4
2B3 54
3
CLKEN Clock Enable (Active Low) GND
GND
4 53
2B2 2B5
5 52
A,1B,2B 3-State Outputs
2B1 2B6
6 51
GND Ground
V V
CC 7 50 CC
VCC Power
A1 2B7
8 49
A2 2B8
9 48
(1)
Truth Tables
A3 2B9
10 47
56-Pin
Output Enable GND GND
11 46
A, V
A4 2B10
12 45
ISNPUTS OUTPUT
2B11
A5 13 44
A6 14 43 2B12
CALKOBE OAE 1B,2B
A7 15 42 1B12
A8 16 41 1B11
HH Z Z
A9 17 40 1B10
HL Z Active
GND 18 39 GND
A10 19 38 1B9
LH AZctive
A11 20 37 1B8
A12 21 36 1B7
LL Aective Activ
22 35 V
V
CC CC
23 34 1B6
1B1
A to B STORAGE (OEB = L)
24 33
1B2 1B5
ISNPUTS OUTPUT
25 32
GND GND
C2LKENA1CKLKENA CAL 1BB 2 26 31
1B3 1B4
(3) (3) CLKEN2B 27 30 CLKENA1
HH X X 1B0 2B0
SEL 28 29 CLK
(2)
LL LL X
(2)
LL HH X
XL LX L
XL HX H
B to A STORAGE (OEA = L)
INPUTS
Outputs
A
CBLKEN1BCKLKEN2CLL SBE 1B2
(3)
HX XHXX A0
(3)
XH XLXX A0
LX HL X L
LX HH X H
XL LX L L
XL LX H H
Notes:
1. H = High Signal Level, L = Low Signal Level
X = Irrelevant, Z = High Impedance
= Transition, Low to High
2. Two CLK edges are needed to propagate data
3. Output level before the indicated steady state input conditions
were established.
PS8352A 07/22/05
06-0138
2