TTMM Application Specific Crystal Oscillator 5.0 x 3.2mm 3.3V HCSL Low Jitter 100MHz PCIe 2.0 XO SQPCIE100 ASSP XO for Networking 5.0 x 3.2mm Ceramic SMD Package: Recommended Land Pattern: Product Features Provides 100 MHz HCSL output for interfacing to standard PCIe devices Very low PCIe 2.0 jitter - 1.8ps RMS (typ.) Thicker crystal for improved reliability Pb-free & RoHS compliant Industrial temperature range CREATED USING CADSTD LITE FREEWARE FROM WWW.CADSTD.COM. NON-COMMERCIAL USE ONLY. Product Description The SQPCIE100 3.3V crystal clock oscillator achieves superb jitter for PCIe 1.0 & 2.0 applications. The output clock Pin Functions: signal, generated internally with a patented Pin Function oscillator design, is compatible with HCSL 1 OE Function logic levels. The device, available on tape 2 N/C and reel, is contained in a 5.0 x 3.2mm 3 V EE surface-mount ceramic package. 4 OUT 5 OUT Applications 6 V CC Server Network Switch/Router CREATED USING CADSTD LITE FREEWARE FROM WWW.CADSTD.COM. NON-COMMERCIAL USE ONLY. *Extended high frequency power decoupling is recommended (see test circuit for minimum Telecom Switch recommendation). To ensure optimal performance, do not route RF traces beneath the Media Box package. Graphics Card Host Bus Adapter Part Ordering Information: SQPCIE100 SaRonix-eCera is a Pericom Semiconductor company US: +1-408-435-0800 TW: +886-3-4518888 www.pericom.com 11-0009 All specifications are subject to change without notice. SQPCIE100 Rev 05 03/16/11 13.3V HCSL Low Jitter 100 MHz PCIe 2.0 XO SQPCIE100 TM Application Specific Crystal Oscillator 5.0 x 3.2mm Electrical Performance Parameter Min. Typ. Max. Units Notes Output Frequency 100 MHz Supply Voltage 2.97 3.30 3.63 V Supply Current, Output Enabled 40 mA Supply Current, Output Disabled 10 mA Frequency Stability 50 ppm See Note 1 below Operating Temperature Range -40 +85 C Industrial Output Logic 0, V -0.15 V OL Output Logic 1, V 0.9 V OH Output Load R = 33, R = 50, C = 2pF Typ., HCSL Termination s p L Duty Cycle 45 55 % Measured 50% of waveform Maximum measured from Rise and Fall Time 0.7 ns V = 0.175V to V = 0.525V OL OH As defined by PCI-SIG for PCIe 2.0 Jitter, Phase RMS (1-) 1.8 2.5 ps reference clock 40 ps 100,000 random periods Jitter, pkpk Notes: 1. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25C), aging (5 year at 40C average effective ambient temperature), shock and vibration. 2. For specifications othere than those listed, please contact sales. Output Enable / Disable Function Parameter Min. Typ. Max. Units Notes Input Voltage (pin 1), Output Enable 0.7*V V or open DD Input Voltage (pin 1), Output Disable (low power standby) 0.3*V V Outputs disabled to Hi-Z DD Output Disable Delay 200 ns Output Enable Delay 2 ms Absolute Maximum Ratings Parameter Min. Typ. Max. Units Notes Storage Temperature -55 +125 C For the latest product information visit: