5962-87628012A E2v

REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED Add vendor CAGE 92527. Page 5: Changes to electrical in table I. Editorial A 88-03-28 Michael A. Frye changes throughout. Add vendor CAGE 75569 for device type 01. Add device type 02. Delete B vendor CAGE 92527. Add case outline S for device types 01 and 02. Editorial 89-01-03 Michael A. Frye changes throughout. Technical changes in figure 2. Technical changes in table I. Add vendor CAGE 27014 and 9Z527 for device C type 01. Add vendor CAGE 75569 for device type 02 and 01SX. Editorial 89-11-29 Michael A. Frye changes throughout. - mbk Update the boilerplate to current requirements as specified in MIL-PRF-38535. D 06-07-11 Thomas M. Hess Editorial changes throughout. jak Correct test condition for total supply current (I ) and add footnote 5/ in CCT E table I. Update boilerplate paragraphs as specified in current requirements of 09-12-24 Thomas M. Hess MIL-PRF-38535. MAA. REV SHEET REV SHEET REV STATUS REV E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Marcia B. Kelleher DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 STANDARD MICROCIRCUIT 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87628 01 R A Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54FCT374 Octal non-inverting D-type flip-flop with three-state outputs, TTL compatible inputs 02 54FCT374A Octal non-inverting D-type flip-flop with three-state outputs, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (V ) ........................................................................... -0.5 V dc to +6.0 V dc CC DC input voltage range (V ) ......................................................................... -0.5 V dc to V + 0.5 V dc IN CC DC output voltage range (V ) .................................................................... -0.5 V dc to V + 0.5 V dc OUT CC DC input diode current (I ) ........................................................................... -20 mA IK DC output diode current (I ) ........................................................................ -50 mA OK DC output current (I ) ................................................................................ 100 mA OUT Maximum power dissipation (P ) 2/ .............................................................. 500 mW D Thermal resistance, junction-to-case ( ) .................................................... See MIL-STD-1835 JC Storage temperature range (T ) ................................................................ -65C to +150 C STG Junction temperature (T ) ............................................................................. +175C J Lead temperature (soldering, 10 seconds) ................................................... +300C 1.4 Recommended operating conditions. 1/ Supply voltage range (V ) ........................................................................... +4.5 V dc to +5.5 V dc CC Maximum low level input voltage (V )........................................................... 0.8 V IL Minimum high level input voltage (V ) .......................................................... 2.0 V IH Case operating temperature range (T ) ........................................................ -55C to +125 C C Minimum setup time, Dn to CP (t ) ................................................................ 2.5 ns s Minimum hold time, Dn to CP (t ) .................................................................. 2.5 ns h Minimum clock pulse width (t ) ..................................................................... 7.0 ns w 1/ Unless other wise specified, all voltages are referenced to ground. 2/ Must withstand the added P due to short circuit test e.g., I . D OS SIZE STANDARD 5962-87628 A MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 E 2 DSCC FORM 2234 APR 97