5962-8872401LA E2v

REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change to vendor similar part number. Change to table I. Removed 90-02-26 M. A. Frye programming procedures for method A, programming waveforms, table III, and ESDS from the drawing. Removed final electrical test from table II. Added device type 04. Editorial changes throughout. B Changes in accordance with NOR 5962-R059-96. 96-03-13 M. A. Frye C Update drawing to current requirements. Editorial changes 01-11-05 Raymond Monnin throughout. - gap D Boilerplate update, part of 5 year review. ksr 07-04-02 Robert M. Heber REV SHEET REV SHEET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS CHECKED BY COLUMBUS, OHIO 43218-3990 STANDARD 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88724 01 K A Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function t PD 01 C22V10L 22-input 10-output 25 ns AND-OR-logic array 02 C22V10L 22-input 10-output 30 ns AND-OR-logic array 03 C22V10L 22-input 10-output 40 ns AND-OR-logic array 04 C22V10L 22-input 10-output 20 ns AND-OR-logic array 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package 1/ L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1/ 3 CQCC1-N28 28 Leadless chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltage range ..................................................................................... -0.5 V dc to +7.0 V dc Input voltage range ....................................................................................... -2.0 V dc to +7.0 V dc 3/ Output voltage applied .................................................................................. -0.5 V dc to +7.0 V dc 3/ Output sink current ........................................................................................ 16 mA Thermal resistance, junction-to-case ( ) .................................................... See MIL-STD-1835 JC Maximum power dissipation (P ) 4/ .............................................................. 1.2 W D Maximum junction temperature ..................................................................... +175C Lead temperature (soldering, 10 seconds maximum) ................................... +300C 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ All voltages referenced to V . SS 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is V +0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. CC 4/ Must withstand the added P due to short circuit test e.g., I . D OS SIZE STANDARD 5962-88724 A MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 D 2 DSCC FORM 2234 APR 97