1CY 7C34 2B fax id: 6107 CY7C342B 128-Macrocell MAX EPLDs The 128 macrocells in the CY7C342B are divided into 8 Logic Features Array Blocks (LABs), 16 per LAB. There are 256 expander 128 macrocells in 8 LABs product terms, 32 per LAB, to be used and shared by the mac- rocells within each LAB. 8 dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. Advanced 0.65-micron CMOS technology to increase performance The speed and density of the CY7C342B allows it to be used in a Available in 68-pin HLCC, PLCC, and PGA wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction Functional Description chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices. By The CY7C342B is an Erasable Programmable Logic Device replacing large amounts of logic, the CY7C342B reduces board (EPLD) in which CMOS EPROM cells are used to configure space, part count, and increases system reliability. logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. Logic Block Diagram 1 (B6) INPUT/CLK INPUT (A7) 68 2 (A6) INPUT INPUT (A8) 66 32 (L4) INPUT INPUT (L6) 36 34 (L5) INPUT INPUT (K6) 35 SYSTEM CLOCK LAB A LABH (B8) 65 4 (A5) MACROCELL 1 MACROCELL 120 5(B4) MACROCELL 2 MACROCELL 119 (A9) 64 (B9) 63 6 (A4) MACROCELL 3 MACROCELL 118 7(B3) MACROCELL 4 MACROCELL 117 (A10) 62 (B10) 61 8 (A3) MACROCELL 5 MACROCELL 116 (B11) 60 9 (A2) MACROCELL 6 MACROCELL 115 (C11) 59 10 (B2) MACROCELL 7 MACROCELL 114 (C10) 58 11 (B1) MACROCELL 8 MACROCELL 113 MACROCELL 9-16 MACROCELL 121-128 LAB B LABG 12 (C2) MACROCELL 101 (D11) 57 MACROCELL 17 13 (C1) (D10) 56 MACROCELL 18 MACROCELL 100 14 (D2) (E11) 55 MACROCELL 19 MACROCELL 99 15 (D1) MACROCELL 98 (F11) 53 MACROCELL 20 17 (E1) (F10) 52 MACROCELL 21 MACROCELL 97 MACROCELL 22-32 MACROCELL 102-112 P I A LAB C LAB F 18 (F2) MACROCELL 33 MACROCELL 85 (G11) 51 19 (F1) (H11) 49 MACROCELL 34 MACROCELL 84 21 (G1) MACROCELL 35 MACROCELL 83 (H10) 48 22 (H2) (J11) 47 MACROCELL 36 MACROCELL 82 23 (H1) MACROCELL 37 MACROCELL 81 (J10) 46 MACROCELL 38-48 MACROCELL 86-96 LAB D LABE MACROCELL 49 MACROCELL 72 (K11) 45 24 (J2) MACROCELL 50 (K10) 44 25 (J1) MACROCELL 71 MACROCELL 51 MACROCELL 70 (L10) 43 26 (K1) (L9) 42 27 (K2) MACROCELL 52 MACROCELL 69 MACROCELL 53 (K9) 41 28 (L2) MACROCELL 68 MACROCELL 54 MACROCELL 67 (L8) 40 29 (K3) (K8) 39 30 (L3) MACROCELL 55 MACROCELL 66 MACROCELL 56 (L7) 38 31 (K4) MACROCELL 65 MACROCELL 73- 80 MACROCELL 57- 64 ( ) PERTAIN TO 68-PIN PGA PACKAGE 3, 20, 37, 54(B5,G2,K7,E10) V CC C342B-1 16, 33, 50, 67 (E2, K5, G10, B7) GND MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor. Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 October 1989 Revised October 1995 CY7C342B Selection Guide 7C342B12 7C342B15 7C342B20 7C342B25 7C342B30 7C342B35 Maximum Access Time (ns) 12 15 20 25 30 35 Maximum Operating Commercial 250 250 250 250 250 250 Current (mA) Military 320 320 320 320 320 Industrial 320 320 320 320 320 Maximum Static Commercial 225 225 225 225 225 225 Current (mA) Military 275 275 275 275 275 Industrial 275 275 275 275 275 Pin Configurations PLCC PGA Top View BottomView L I/O I/O INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O GND INPUT V I/O I/O I/O I/O K I/O I/O CC 98 76534 21 68 67 66 65 64 63 62 61 I/O I/O 10 60 J I/O I/O I/O I/O I/O 11 I/O 59 I/O 12 I/O 58 H I/O I/O I/O I/O I/O 13 I/O 57 I/O I/O 14 56 I/O 15 55 I/O V GND I/O G I/O CC GND 54 V 16 CC I/O 53 I/O 17 F I/O I/O I/O I/O I/O I/O 18 52 7C342B I/O I/O 19 51 V GND CC 20 7C342B 50 E I/O GND V I/O CC I/O I/O 21 49 I/O I/O 22 48 I/O I/O I/O I/O I/O D I/O 47 23 I/O I/O 46 24 I/O I/O 45 25 C I/O I/O I/O I/O I/O I/O 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 INPUT/ I/O I/O I/O I/O V GND I/O I/O I/O I/O B CC CLK I/O I/O I/O I/O INPUT INPUT INPUT I/O I/O A C342B-2 12 34 56 7 8 9 10 11 C342B-3 2