1CY7C346B fax id: 6104 CY7C346 CY7C346B 128-Macrocell MAX EPLDs ture is 100% user configurable, allowing the devices to accom- Features modate a variety of independent logic functions. 128 macrocells in 8 LABs The 128 macrocells in the CY7C346/CY7C346B are divided 20 dedicated inputs, up to 64 bidirectional I/O pins into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256 Programmable interconnect array expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. 0.8-micron double-metal CMOS EPROM technology (CY7C346) Each LAB is interconnected through the programmable inter- Advanced 0.65-micron CMOS technology to increase connect array, allowing all signals to be routed throughout the performance (CY7C346B) chip. Available in 84-pin CLCC, PLCC, and 100-pin PGA, The speed and density of the CY7C346/CY7C346B allow it to PQFP be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers Functional Description and multifunction chips. With greater than 25 times the func- tionality of 20-pin PLDs, the CY7C346/CY7C346B allows the The CY7C346/CY7C346B is an Erasable Programmable Log- replacement of over 50 TTL devices. By replacing large ic Device (EPLD) in which CMOS EPROM cells are used to amounts of logic, the CY7C346/CY7C346B reduces board configure logic functions within the device. The MAX architec- space, part count, and increases system reliability. Logic Block Diagram INPUT 59 (N4) . 36 .. 1 (C7) 16 . INPUT/CLK INPUT 60 (M5) . 37 . 78 (A10) 9 ..... INPUT INPUT 61 (N5) . 38 . 79 (B9) 10 ..... INPUT INPUT 64 (N6) . 41 80 (A9) 11 ..... INPUT INPUT 65 (M7) . 42 . 83 (A8) 14 ..... INPUT INPUT 66 (L7) . 43 . 84 (B7) 15 ..... INPUT INPUT 67 (N7) . 44 .. 2 (A7) 17 ..... INPUT INPUT 70 (L8) . 47 .. 5 (C6) 20 ..... INPUT INPUT 71 (N9) . 48 .. 6 (A5) 21 ..... INPUT INPUT 72 (M9) . 49 .. 7 (B5) 22 ..... INPUT SYSTEM CLOCK LAB A LAB H MACROCELL 1 MACROCELL 120 100 (C13) NC 8 (B13) 1 MACROCELL 2 MACROCELL 119 99 (D12) NC 9 (C12) 2 MACROCELL 3 MACROCELL 118 98 (D13) 77 10 (A13) 3 MACROCELL 4 97 (E12) 76 MACROCELL 117 11 (B12) 4 MACROCELL 5 MACROCELL 116 96 (E13) 75 12 (A12) 5 MACROCELL 6 MACROCELL 115 95 (F11) 74 13 (11) 6 MACROCELL 7 92 (G13) 73 NC (A11) 7 MACROCELL 114 MACROCELL 8 91 (G11) 72 NC (B10) 8 MACROCELL 113 MACROCELL 916 MACROCELL 121128 LAB B LAB G 14 (A4) 23 MACROCELL 17 MACROCELL 104 90 (G12) NC MACROCELL 103 15 (B4) 24 MACROCELL 18 89 (H13) NC MACROCELL 102 16 (A3) 25 MACROCELL 19 86 (J13) 71 17 (A2) 26 MACROCELL 20 MACROCELL 101 85 (J12) 70 18 (B3) 27 MACROCELL 21 MACROCELL 100 84 (K13) 69 21 (A1) 28 MACROCELL 22 MACROCELL 99 83 (K12) 68 NC (B2) 29 MACROCELL 98 82 (L13) 67 MACROCELL 23 NC (B1) 30 MACROCELL 24 MACROCELL 97 81 (L12) 64 MACROCELL 105112 MACROCELL 2532 P I LAB C A LAB F MACROCELL 33 22 (C2) 31 MACROCELL 88 80 (M13) NC MACROCELL 34 25 (C1) 32 MACROCELL 87 79 (M12) NC 26 (D2) 33 MACROCELL 35 78 (N13) 63 MACROCELL 86 27 (D1) 34 MACROCELL 36 77 (M11) 60 MACROCELL 85 28 (E2) 35 MACROCELL 37 76 (N12) 59 MACROCELL 84 MACROCELL 38 29 (E1) 36 MACROCELL 83 75 (N11) 58 MACROCELL 39 NC (F1) 39 MACROCELL 82 74 (M10) 57 NC (G2) 40 MACROCELL 40 73 (N10) 56 MACROCELL 81 MACROCELL 4148 MACROCELL 8696 LAB D LAB E MACROCELL 49 58 (M4) NC 30 (G3) 41 MACROCELL 72 MACROCELL 50 31 (G1) 42 MACROCELL 71 57 (N3) NC MACROCELL 51 MACROCELL 70 56 (M3) 55 32 (H3) 45 MACROCELL 52 55 (N2) 54 33 (J1) 46 MACROCELL 69 MACROCELL 53 54 (M2) 53 34 (J2) 47 MACROCELL 68 MACROCELL 54 53 (N1) 52 35 (K1) 48 MACROCELL 67 MACROCELL 55 52 (L2) 51 NC (K2) 49 MACROCELL 66 MACROCELL 56 NC (L1) 50 MACROCELL 65 51 (M1) 50 MACROCELL 73 80 MACROCELL 57 64 ( ) PERTAIN TO 100PIN PGA PACKAGE 3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) 18, 19, 43, 44, 68, 69, 93, 94 V CC PERTAIN TO 100PIN PQFP PACKAGE C3461 16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) 12, 13, 37, 38, 62, 63, 87, 88 GND Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 October 1989 Revised March 31, 1997 CY7C346 CY7C346B Selection Guide 7C34625 7C34630 7C34635 7C346B15 7C346B20 7C346B25 7C346B30 7C346B35 Maximum Access Time (ns) 15 20 25 30 35 Maximum Operating Commercial 250 250 250 250 250 Current (mA) Military 320 325 320 320 Industrial 320 320 320 320 320 Maximum Standby Commercial 225 225 225 225 225 Current (mA) Military 275 275 275 275 Industrial 275 275 275 275 275 Shaded area contains preliminary information. Pin Configurations PLCC/CLCC PGA Top View BottomView 79 78 77 76 10 98 76453 21 84 83 82 81 80 75 11 I/O I/O I/O INP INP INP INP V INP I/O I/O I/O I/O N CC I/O 12 I/O 74 I/O I/O I/O I/O INP GND INP V INP I/O I/O I/O I/O M CC 13 I/O 73 I/O 14 I/O 72 I/O I/O I/O GND INP INP I/O I/O L 15 I/O 71 I/O I/O 16 70 I/O I/O I/O I/O I/O K 69 I/O 17 I/O I/O 18 68 I/O I/O I/O I/O I/O J GND 19 67 I/O V V I/O GND GND I/O GND H CC CC 20 66 V CC I/O 21 65 V CC 7C346 I/O I/O I/O I/O I/O I/O G I/O 22 7C346B 64 I/O V CC 23 63 I/O I/O GND GND I/O V F CC V 7C346 CC V 24 CC 62 GND 7C346B I/O 25 I/O I/O I/O I/O 61 GND E 26 I/O 60 I/O I/O I/O I/O I/O I/O D 27 59 I/O I/O 28 58 I/O INP I/O I/O INP GND I/O I/O I/O C 29 57 I/O /CLK I/O 30 56 I/O I/O I/O I/O I/O INP V INP GND INP I/O I/O I/O I/O B CC I/O 31 55 I/O I/O 32 I/O 54 I/O I/O I/O I/O INP V INP INP INP INP I/O I/O I/O A CC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1 2 3 4 5 6 7 8 9 10 11 12 13 C3463 C3462 2