PC755/745 PowerPC755/745RISCMicroprocessor DatasheetDS0828 Thisdocumentdescribespertinentphysicalcharacteristics FEATURES ofthePC755.ForinformationonspecificPC755part 18.1SPECint95,Estimates12.3SPECfp95at400MHz(PC755) numberscoveredbythisorotherspecifications,see 15.7SPECint95,9SPECfp95at350MHz(PC745) Table 111,OrderingInformation,onpage 60.For 733MIPSat400MHz(PC755)at641MIPSat350MHz functionalcharacteristicsoftheprocessor,refertothe (PC745) MPC750RISCMicroprocessorFamilyUsersManual. SelectableBusClock(12CPUBusDividersupto10x) Tolocateanypublishederrataorupdatesforthisdocu P Typical5.4Wat400MHz,FullOperatingConditions D ment,refertothewebsitelistedonthebackcoverofthis Nap,DozeandSleepModesforPowerSavings document. Superscalar(3InstructionsperClockCycle)TwoInstruction+ Branch 4BetaByteVirtualMemory,4GByteofPhysicalMemory Screening 64bitDataand32bitAddressBusInterface Thisproductismanufacturedinfullcompliancewith: 32KBInstructionandDataCache HiTCECBGAAccordingtoe2vStandards SixIndependentExecutionUnits CBGA+CICGA+FCPBGAupScreeningsBasedupone2v WritebackandWritethroughOperations Standards f max=400MHz INT FullMilitaryTemperatureRanges(T =55C,T =+125C) C J f max=100MHz BUS IndustrialTemperatureRanges(T =40C,T =+110C) C J VoltageI/O2.5V/3.3V VoltageInt2.0V CommercialTemperatureranges(T =0C,T =+105C) C J Description ThisdocumentisprimarilyconcernedwiththePC755 however, unlessotherwisenoted,allinformationherealsoappliestothe PC745.ThePC755andPC745arereducedinstructionsetcom puting(RISC)microprocessorsthatimplementthePowerPC instructionsetarchitecture. Whilste2vtechnologieshastakencaretoensuretheaccuracyoftheinformationcontainedhereinitacceptsnoresponsibilityfortheconsequencesofany usethereofandalsoreservestherighttochangethespecificationofgoodswithoutnotice.e2vtechnologiesacceptsnoliabilitybeyondthesetoutinits standardconditionsofsaleinrespectofinfringementofthirdpartypatentsarisingfromtheuseofdevicesinaccordancewithinformationcontained herein. e2vtechnologies(uk)limited,WaterhouseLane,Chelmsford,EssexCM12QUUnitedKingdomHoldingCompany:e2vtechnologiesplc Telephone:+44(0)1245493493Facsimile:+44(0)1245492492 Contacte2vbyemail:enquiries e2v.comorvisitwww.e2v.comforglobalsalesandoperationscentres. 0828OHIREL01/17 e2vtechnologies(uk)limited2017PC755/745 1. OVERVIEW ThePC755istargetedforlowcost,lowpowersystemsandsupportsthefollowingpowermanagement features:doze,nap,sleep,anddynamicpowermanagement.ThePC755consistsofaprocessorcore andaninternalL2tagcombinedwithadedicatedL2cacheinterfaceanda60xbus.ThePC745is identicaltothePC755exceptitdoesnotsupporttheL2cacheinterface. Figure11showsablockdiagramofthePC755. Figure11. PC755BlockDiagram 128-Bit Instruction Unit (4 Instructions) Branch Processing Fetcher Unit Instruction MMU Additional Features CTR BTIC * Time Base Counter/Decrementer LR Instruction Queue 64-Entry SRs * Clock Multiplier (6-Word) (Shadow) IBAT 32-Kbyte * JTAG/COP Interface BHT Tags Array I Cache * Thermal/Power Management ITLB * Performance Monitor 2 Instructions 64-Bit Dispatch Unit (2 Instructions) Reservation Station Reservation Station Reservation Station Reservation Station Reservation Station GPR File FPR File (2-Entry) Rename Buffers Rename Buffers (6) (6) System Register 32-Bit 64-Bit 64-Bit Load/Store Unit Floating-Point Integer Unit 1 Integer Unit 2 Unit Unit + + x : (EA Calculation) + + x : CR Store Queue FPSCRFPSCR 32-Bit 32-Bit PA EA 60x Bus Interface Unit Completion Unit Data MMU 64-Bit Instruction Fetch Queue L2 Bus Interface Reorder Buffer Unit SRs L1 Castout Queue (6-Entry) (Original) DBAT L2 Castout Queue 32-Kbyte Array Tags Data Load Queue L2 Controller D Cache DTLB L2CR L2 Tags 32-Bit Address Bus 32-/64-Bit Data Bus Not in the PC745 17-Bit L2 Address Bus 64-Bit L2 Data Bus 2 0828OHIREL01/17 e2vtechnologies(uk)limited2017