TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated) P Typically = 3.5W (266 MHz), Full Operating Conditions D Branch Folding 64-bit Data Bus (32-bit Data Bus Option) 4-Gbytes Direct Addressing Range Pipelined Single/Double Precision Float Unit IEEE 754 Compatible FPU IEEE P 1149-1 Test Mode (JTAG/C0P) f Max = 300 MHz INT f Max = 75 MHz BUS Compatible CMOS Input/TTL Output Features Specific to Cerquad 5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated) P Typically = 2.5W (200 MHz), Full Operating Conditions D Visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors SAS 2011 0841DHIREL05/11TSPC603R 1. Description The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power imple- mentation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. The 603R is a low-power 2.5/3.3V design and provides four software controllable power-saving modes. This device is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can be executed in any order for increased performance, but, the 603R makes com- pletion appear sequential. It integrates five execution units and is able to execute five instructions in parallel. The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instructions, and data Memory Management Units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look aside buffers that provide support for demand-paged virtual memory address translation and vari- able-sized block translation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The interface protocol allows multiple masters to compete for system resources through a central exter- nal arbiter. The device supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/Os. The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compati- bility with TTL devices. It also integrates in-system testability and debugging features through JTAG boundary-scan capabilities. 2. Screening/Quality/Packaging This product is manufactured in full compliance with: HiTCE CBGA according to e2v Standards CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to e2v standards CBGA 255: Upscreenings based upon e2v standards CBGA, CI-CGA, HiTCE packages: Full military temperature range (T = -55C, T = +125C) C j Industrial temperature range (T = -40C, T = +110C) C j Cerquad: Full military temperature range (T = -55C, T = +125C) C c Industrial temperature range (T = -40C, T = +110C) C c Commercial temperature ranges (T = 0 C, T = +70 C) C C Internal I/O Power Supply = 2.5 5% // 3.3V 5% 2 0841DHIREL05/11 e2v semiconductors SAS 2011