LPC81xM 32-bit ARM Cortex -M0+ microcontroller up to 16 kB flash and 4 kB SRAM Rev. 4.7 19 March 2021 Product data sheet 1. General description The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM. 2 The peripheral complement of the LPC81xM includes a CRC engine, one I C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. 2. Features and benefits System: ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. Serial Wire Debug (SWD) and JTAG boundary scan modes supported. Micro Trace Buffer (MTB) supported. Memory: Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase. Up to 4 kB SRAM. ROM API support: Boot loader. USART drivers. I2C drivers. Power profiles. Flash In-Application Programming (IAP) and In-System Programming (ISP). Digital peripherals: High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and glitch filter. High-current source output driver (20 mA) on four pins. High-current sink driver (20 mA) on two true open-drain pins. GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs. Switch matrix for flexible configuration of each I/O pin function.NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller State Configurable Timer/PWM (SCTimer/PWM) with input and output functions (including capture and match) assigned to pins through the switch matrix. Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates. Self Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator. CRC engine. Windowed Watchdog timer (WWDT). Analog peripherals: Comparator with internal and external voltage references with pin functions assigned or enabled through the switch matrix. Serial interfaces: Three USART interfaces with pin functions assigned through the switch matrix. Two SPI controllers with pin functions assigned through the switch matrix. 2 One I C-bus interface with pin functions assigned through the switch matrix. Clock generation: 12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be used as a system clock. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz. 10 kHz low-power oscillator for the WKT. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input CLKIN, or the internal RC oscillator. Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control: Integrated PMU (Power Management Unit) to minimize power consumption. Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and I2C peripherals. Timer-controlled self wake-up from Deep power-down mode. Power-On Reset (POR). Brownout detect. Unique device serial number for identification. Single power supply. Operating temperature range 40 C to 105 C except for the DIP8 package, which is available for a temperature range of 40 C to 85 C. Available as DIP8, TSSOP16, SO20, TSSOP20, and XSON16 package. 3. Applications 8/16-bit applications Lighting Consumer Motor control Climate control Fire and security applications LPC81XM All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2021. All rights reserved. Product data sheet Rev. 4.7 19 March 2021 2 of 78