GRAPHICS S1D13513 S1D13513 Display Controller August 2007 The S1D13513 is a highly integrated Display Controller capable of outputting to LCD or TV. With the flexibility of an external SDRAM memory interface, this low cost, low power, device supports a wide range of CPUs, panels, and a camera port that can be configured as 2x 8-bit ports. The S1D13513 feature set and architecture are designed to meet the requirements of embedded systems such as Mobile Communications, Hand-Held PCs, Office Automation, and Automotive applications. The S1D13513 features both Sprite and 2D BitBLT engines designed to reduce the load on the Host, while increasing the performance of graphics intensive operations. Additionally, the S1D13513 offers such features as multiple windows, alpha blending, gamma correction, and mirror/rotation function which allow user configurability of various images on the Main/PIP1/PIP2 displays. While focusing on devices targeted by the Microsoft Windows CE Operating System, the S1D13513s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. FEATURES Direct and Indirect CPU interfaces Dual port Camera interface with resize function Serial Host Interface Sprite Engine Memory interface for x16 or x32 external SDRAM (x32 2D Hardware Acceleration Engine available on S1D13513 PBGA only) Overlay features Programmable resolutions and color depths Multiple Windows (Layers) with Alpha Blending Support for single RGB panel with serial command inter- Gamma Correction face 4 Channel PWM for Backlight control YUV DIgital Output (YUV 4:2:2) which supports Keypad Interface with 5x5 matrix support NTSC/PAL TV output via an external video encoder Software initiated Power Save Mode Clocks can be selected from two embedded PLLs or Low Operating Voltage digital clock inputs Package: PBGA 256-pin and QFP 208-pin (QFP does not Two built-in Crystal inputs support all features) SYSTEM BLOCK DIAGRAM Keypad Interface Camera Interface (dual port) Display (RGB with SCI) SDRAM 13513 Optional TV support Memory External Data and Video Control Signals Encoder S1D13513 Includes: 2D Hardware Acceleration Host Sprite Engine CPU 4 channel PWM Keypad Interface 2 PLLs or digital clock inputs X78B-C-001-01 1 Revision 1.01GRAPHICS S1D13513 DESCRIPTION External Display Buffer CPU Interface Uses external SDRAM or mobile SDRAM as display buffer Direct and indirect interface support for most popular CPU inter- Supports x16 / x32 SDRAM interface (Size: 8M byte, 16M byte, faces 32Mbyte or 64Mbyte) (x32 and 32/64Mbyte not supported for Serial Host Interface QFP package) Supports 20-50MHz Host bus clock SDRAM clock: 100MHz Maximum Registers are memory-mapped - M/R input selects between Automatic re-entry into self refresh mode memory and register address space Provides linear access to first 1M bytes and four configurable 256KB windows into the remaining memory Digital Video Dual Camera / Video Input port can be configured as 2x 8-bit Display Support camera ports RGB Interface single panel Supports ITU-R BT656 (CCIR-656) YUV format 16/18/24-bit Color TFT (24-bit not supported for QFP) Supports resize function of the video in stream Optional serial command interface Supports raw JPEG capture from JPEG capable camera 8-bit Monochrome passive panel Captures YUV data into SDRAM as YUV 4:2:2 format 8-bit Color Type 2 passive panel View Image can be displayed to LCD or TV YUV Digital Output (YUV 4:2:2) which supports NTSC/PAL TV Resize function built-in for both View and Capture path Output via an external Video Encoder Color Depths up to 32 bpp Acceleration Example resolutions 2D BitBLT Engine (Read, Write, Move, and Fill BLTs) 1024x768 at a color depth of 16 bpp (x32 SDRAM only) 2D Sprite Engine (up to 16 sprites) 800x600 at a color depth of 16 bpp (x32 SDRAM only) Unified Command FIFO for both BitBLT and Sprite 640x480 at a color depth of 32 bpp (x32 SDRAM only) Miscellaneous Display Features Internal system clock: 50MHz maximum (half of SDRAM clock) Multiple window (layer) support 4 channel PWM for backlight control Mirror and 180 rotation functions I2C Interface (typically used for camera) Double Buffering support Keypad Interface with 5 x 5 matrix support Alpha Blending Software initiated power save mode Gamma Correction Multiple General Purpose IO pins Pseudo Color Expansion Flexible clock structure: Hardware cursor support via the Sprite engine Two embedded PLLs Camera image can be displayed on the PIP1/PIP2 window Two built-in crystal inputs Interrupts available Four digital clock inputs Supports maskable non-display (Vsync) interrupt Clocks dynamically turned off when modules are not needed Supports delayed version of Vsync Interrupt CORE 1.8 volts and IO 3.3 volts VDD VDD Package: PBGA 256-pin and QFP 208-pin CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13513 Technical CPU Independent S1D13513 Evaluation Royalty Free source level Documentation Software Utilities Boards driver code Japan Taiwan North America Seiko Epson Corporation Epson Taiwan Technology & Trading Ltd. Epson Electronics America, Inc. IC International Sales Group 14F, No. 7 2580 Orchard Parkway 421-8, Hino, Hino-shi Song Ren Road San Jose, CA 95131, USA Tokyo 191-8501, Japan Taipei 110 Tel: (408) 922-0200 Tel: 042-587-5812 Tel: 02-8786-6688 Fax: (408) 922-0238 Fax: 042-587-5564 Fax: 02-8786-6677