GRAPHICS S1D13742 S1D13742 Mobile Graphics Engine August 2007 The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates. Products requiring a rotated display image can take advantage of the SwivelView feature which provides hardware rotation of the display memory transparent to the software application. Resolutions supported include 800x480 single buffered and 352x416 double buffered. The S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. FEATURES Embedded 768K byte SRAM Display Buffer 16/18 bit-per-pixel (bpp) color depths. Low Operating Voltage SwivelView: 90, 180, 270 counter-clockwise hardware rotation of display image 8/16-bit Intel 80 interface (used for display or regis- ter data). Double-Buffer available to prevent image tearing during streaming input RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). Pixel Doubling: Horizontal and Vertical averaging for smooth doubling of a single window YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp). Pixel Halving: no limitation on number of windows Active Matrix TFT interface - 18/36-bit interface. Internal programmable PLL. Supports resolutions up to 800x480. Single MHz clock input: CLKI. Hardware / Software Power Save mode. General Purpose Input/Output pins. SYSTEM BLOCK DIAGRAM Active Matrix TFT Display 13742 Data and Control Signals S1D13742 Includes: 768K Bytes SRAM Pixel Doubling Pixel Halving CPU Swivelview X63A-C-001-03 1 Revision 3.01GRAPHICS S1D13742 DESCRIPTION Integrated Frame Buffer Digital Video Embedded 768K byte SRAM display buffer. RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). CPU Interface YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp). 8/16-bit Intel 80 interface (used for display or register data). Display Features Chip select is used to select device. When inactive, any input data/command will be ignored. 16/18 bit-per-pixel (bpp) color depths. 16 bpp to 18 bpp Input Data conversion. Panel Support All display writes are handled by window apertures/position Active Matrix TFT interface. for complete or partial display updates. All window coordi- nates are referenced to top left corner of the displayed image 18/36-bit interface. (even in a rotated display, the top-left corner is maintained Supports resolutions up to 800x480. and no host side translation need take place). Miscellaneous SwivelView: 90, 180, 270 counter-clockwise hardware rotation of display image. All displayed windows can have Internal programmable PLL. independent rotation. No additional programming necessary Single MHz clock input: CLKI. when enabling these modes. CLKI available as CLKOUT (separate CLKOUTEN pin Double-Buffer available to prevent image tearing during associated with output). streaming input. Resolutions supported must fit inside 384K Hardware / Software Power Save mode. bytes ( of total available display buffer). Typical resolution of Input pin to Enable/Disable Power Save Mode. 352x416. General Purpose Input/Output pins are available Pixel Doubling: Horizontal and Vertical averaging for smooth (GPIO 7:0 ). doubling of a single window. COREVDD 1.5 volts and IOVDD 1.65 ~ 3.6 volts Pixel Halving: no limitation on number of windows. FCBGA 121-pin or QFP20 144-pin package CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13742 Technical CPU Independent Documentation Software Utilities S1D13742 Evaluation Royalty Free source level Boards driver code Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology & Trading Ltd. IC International Sales Group 2580 Orchard Parkway 14F, No. 7 421-8, Hino, Hino-shi San Jose, CA 95131, USA Song Ren Road Tokyo 191-8501, Japan Tel: (408) 922-0200 Taipei 110 Tel: 042-587-5812 Fax: (408) 922-0238 Tel: 02-8786-6688 Fax: 042-587-5564