GRAPHICS S1D13746 S1D13746 TV-Out Graphics Engine August 2007 The S1D13746 is an extremely low cost, low pin-count device providing direct support for TV from a standard memory-mapped frame-buffer. Internal high quality scaling algorithms allow for low resolution input to be smoothly scaled to the full resolution as determined by either PAL or NTSC standards. The S1D13746 is the ideal solution for cellular phone markets where TV-output is a requirement. The S1D13746 contains 312K bytes of embedded SRAM. Input data can be double-buffered, thereby acting as a frame rate converter and preventing any visual tearing during streaming input. The minimal feature set and high level of integration (embedded high output DAC) provides a low cost, low power, single chip solution to meet the demands of embedded markets requiring Digital Video, such as Mobile Communications devices. FEATURES Embedded 312K byte SRAM Bi-Cubic Scalar from input to output Double-buffered for streaming video PAL and NTSC output Low Operating Voltage Automatic Border Serial / Parallel Host Interface Auto-Centering Parallel RGB Interface Destructive Windows (Overlays) with transparency function Multiple Input Data formats Software Initiated Power Save Mode High Output DAC Internal PLL or Digital Clock Input Input Image Rotation (SwivelView 90/180/270) SYSTEM BLOCK DIAGRAM direct TV-out 13746 CPU TV Display 720x576 Original TV Image (written to memory) Scaled to fit X74A-C-001-01 1 Revision 1.03GRAPHICS S1D13746 DESCRIPTION Integrated Frame Buffer TV Output 312K byte SRAM Composite PAL/NTSC output S-Video PAL/NTSC output CPU Interface Programmable Chrominance / Luminance Filters Parallel Indirect Interface (Intel 80) 3x3 Pixel filter Serial Interface Auto-Border / Auto-Center 3-wire (9-bit) Wide-Screen Signalling Support (ETSI EN 300 294 com- 4-wire (8-bit SPI) pliant) Parallel RGB Interface Closed Caption Support (CEA-608-B) Macrovision Protection support (bond out option) Input Formats Test Pattern Generator RGB: 3:3:2, 5:6:5, 6:6:6, 8:8:8 Supports Destructive Windows (overlays) with YUV: 4:2:0, 4:2:2 transparency function All input formats are converted and stored as YUV 4:2:0 Miscellaneous Input image can be rotated (SwivelView 90/180/270) Internal PLL or digital clock input Input Scalar Software initiated power save mode Bi-Cubic, 9-bit, non-integer based CORE 1.5 Volts and IO 1.8 to 3.3 Volts VDD VDD Arbitrary Horizontal / Vertical settings Package: PFBGA 100-pin (7mm x 7mm) Automatic scaling based on input/output window settings THEORY OF OPERATION The S1D13746 contains its own frame-buffer memory where image data can be stored and displayed from. Input images larger than the memory size are automatically scaled down using a Bi-cubic method before being stored. All images can be stored using a double-buffered architecture to prevent any visual tearing and act as a rate converter. All stored images can be further scaled up/down for display on the TV. If the resulting scaled image does not fit the maximum resolution as defined by the TV standard, the image is auto-centered and bordered. The 3x3 pixel filter and programmable chrominance / luminance filters are provided to generate a high quality resulting image. The S1D13746 supports Wide-Screen Signalling, Closed Captioning, includes a built-in Test Pattern Generator, and has a bond-out option available for Macrovision Protection . CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13746 Technical CPU Independent S1D13746 Evaluation Royalty Free source level Documentation Software Utilities Boards driver code Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology & Trading Ltd. IC International Sales Group 14F, No. 7 2580 Orchard Parkway 421-8, Hino, Hino-shi San Jose, CA 95131, USA Song Ren Road Tokyo 191-8501, Japan Tel: (408) 922-0200 Taipei 110 Tel: 042-587-5812 Fax: (408) 922-0238 Tel: 02-8786-6688 Fax: 042-587-5564