GRAPHICS S1D13748 S1D13748 Mobile Graphics Engine October 2007 The S1D13748 is a low cost, low power Mobile Graphics Engine providing multiple LCD support for embedded and mobile products requiring up to WVGA resolution. Supporting up to three display layers, the S1D13748 provides the Host processor with flexibility in handling multiple image sources. Its ability to receive high speed Host writes, combined with its support for a wide variety of LCD panels, makes the S1D13748 an excellent choice for a multitude of LCD applications. The S1D13748 includes a pixel doubling feature which allows easy migration to larger panel sizes using existing image data. The feature set includes independent resizing of PIP window image data using the bi-cubic scaler, scrolling control for each layer, and LCD output manipulation such as gamma control and optional dithering. This allows the Host processor to provide image data, but off-loads the image processing requirement from the Host. The S1D13748 also incorporates LCD Bypass Mode which allows the Host to exercise direct control over parallel or serial RAM-based panels. The S1D13748 contains 1024K bytes of embedded SRAM which is used to store image data for up to three layers for LCD1 and image data for LCD2. This feature set provides a low cost, low power single chip solution to meet the demands of embedded markets requiring up to WVGA resolution, such as Mobile Communications devices. FEATURES Embedded 1024K byte SRAM Support for up to 3 display layers with overlay and alpha blending Low Operating Voltage Main Layer image can be doubled in size 16-bit Indirect Host Interface PIP1 Layer can be resized from 8x to 1/8x High Speed Host Writes PIP2 Layer can be resized from 8x to 1/8x Rectangular, Rotated, and Mirror Host Write Modes Independent scrolling control for each layer Input Formats: YUV 4:2:2, 4:2:0 and RGB 5:6:5 Look-up Table for gamma control of LCD output Supports up to 2 LCD panels (LCD2 must be RAM Optional dithering of LCD output integrated) Internal PLL or Digital Clock Input Support for RGB, Serial, and Parallel I/F panels Software Initiated Power Save Mode LCD Bypass Mode PFBGA 121-pin or QFP20 144-pin packages SYSTEM BLOCK DIAGRAM Main Display Secondary Display RGB or Parallel 13748 Serial or Parallel (Ram Integrated) Data and Control Signals S1D13748 Includes: 1024KB SRAM Up to 3 Display Layers Overlay and Alpha Blending CPU Display Scrolling Gamma Control of LCD output X80A-C-001-01 1 Revision 1.03GRAPHICS S1D13748 DESCRIPTION Memory Display Features 1024K bytes of embedded SRAM Supports up to 3 layers with Overlay and Alpha Blending functions: CPU Interface Main Layer features: 16-bit Indirect Host Interface Image can be stored as RGB 5:6:5 Supports High Speed Host Writes Pixel Doubling which doubles the size of the display Integrated Host interface Write Controller supports: image (independent horizontal/vertical) Rectangular Write Mode PIP1 Layer features: Rotated Write Mode Image can be stored as RGB 5:6:5 or YUV 4:2:2 Mirror Write Mode Bi-Cubic Scaler can resize image from 8x - 1/8x LCD Bypass Mode allows direct control of serial and par- Edge Enhancement support allel LCD panels by the Host CPU PIP2 Layer features: Image can be stored as RGB 5:6:5 or YUV 4:2:2 Panel Support Bi-Cubic Scaler can resize image from 8x - 1/8x 9/12/16/18/24-bit RGB interface panels Panorama function allows variable vertical scaling 8/16/18/24-bit Parallel interface panels (RAM Integrated) Edge Enhancement support 8/16-bit Serial interface panels (RAM Integrated) LUT (Look-Up Table) for independent gamma con- Supports up to 2 LCD panels (LCDs cannot be refreshed trol of PIP2 window simultaneously) Independent Display Scrolling for each Layer (Main, PIP1, LCD1: RGB, LCD2: Serial w/ RAM PIP2) LCD1: Parallel w/ RAM, LCD2: Serial w/RAM LUT (Look-Up Table) for gamma control of the LCD output LCD1: Parallel w/RAM, LCD2: Parallel w/RAM Optional dithering for the LCD output LCD1: RGB, LCD2: Parallel w/RAM Miscellaneous Input Formats Internal PLL or digital clock input (CLKI) Host can input image data as: Software initiated power save mode YUV 4:2:2 General Purpose IO pins YUV 4:2:0 CORE 1.5 volts and IO 1.80, 2.80, or 3.30 volts VDD VDD RGB 5:6:5 Packages: PFBGA 121-pin (10 x 10 x 1.2mm) (0.8mm pitch) QFP20 144-pin (20 x 20 x 1.4mm) (0.5mm pitch) CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13748 Technical CPU Independent S1D13748 Evaluation Royalty Free source level Documentation Software Utilities Boards driver code Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology & Trading Ltd. IC International Sales Group 2580 Orchard Parkway 14F, No. 7 421-8, Hino, Hino-shi San Jose, CA 95131, USA Song Ren Road Tokyo 191-8501, Japan Tel: (408) 922-0200 Taipei 110 Tel: 042-587-5812 Fax: (408) 922-0238 Tel: 02-8786-6688 Fax: 042-587-5564