GRAPHICS S1D13771 S1D13771 TV-Out Graphics Engine August 2007 S1D13771 is an extremely low cost, low pin-count device providing direct support for TV output. A high quality internal scaler and complex TV filters allow for VGA resolution input to be stored using a minimum amount of memory, while still providing smoothly scaled output to the full resolution specified by either PAL or NTSC standards. S1D13771 is the ideal solution for cellular phone markets where TV output is a requirement. The minimal feature set and high level of integration (embedded SRAM and high output DAC) provides a low cost, low power, single chip solution to meet the demands of embedded markets requiring TV output, such as Mobile Communications devices. FEATURES Embedded SRAM TV Connect/Disconnect Detection Low Operating Voltage PAL and NTSC output Parallel Host Interface Auto-Border / Auto-Center of TV Image with a pro- grammable color High Output DAC 15-Tap Programmable Chrominance / Luminance Filters High Quality Scaler provides Bi-Cubic input/output scaling 3x3 Pixel Filter Software Initiated Power Save Mode SYSTEM BLOCK DIAGRAM Direct TV output 13771 CPU Original Image TV Display (written to S1D13771) 720x576 Output is filtered, processed by the scaler, 640x480 Input and output to TV Input is processed by the scaler and stored in internal memory or 720x576 640x480 Output is filtered, processed by the scaler, automatically bordered, and output to TV X82A-C-001-01 1 Revision 1.02GRAPHICS S1D13771 DESCRIPTION Integrated Frame Buffer Image Enhancement Engine Embedded SRAM 3x3 Pixel filter User defined coefficients CPU Interface Individual control for each YUV component 8-bit Parallel Indirect Interface (Intel 80) Display effects include: smooth, sharpen, blur, detail, Chip select is used to select device. When in-active, any edge enhance, emboss, contour, flicker filter, sepia, and input data/commands are ignored. dot crawl correction Input Formats Clock Input RGB: 8:8:8, 6:6:6, 5:6:5 Single digital clock input used for: (18-27MHz typical) YUV: 4:2:2 Internal PLL reference clock (PLL used for system clock) All input data is processed by the scaler and stored in TV Timing (can optionally use PLL2) internal memory. DDS Timing (can optionally use PLL2) TV Output Miscellaneous Composite PAL / NTSC output Power save mode 15-Tap Programmable Chrominance / Luminance Filters Software controllable via registers Scaler uses Bi-Cubic scaling to scale-up or scale-down General purpose IO pins Auto-Border / Auto-Center Configurable interrupt associated with GPIO inputs Programmable border color CORE 1.5 Volts and IO 1.8 to 3.3 Volts VDD VDD Square Pixel Correction DAC power supply: 3.0 Volts Macrovision Protection Support (bond-out option) Package: W-CSP 64-pin (4.46 x 4.46mm) TV Connect/Disconnect Detection THEORY OF OPERATION The S1D13771 contains an embedded SRAM frame buffer allowing up to VGA resolution to be stored using a high quality scaling algorithm. All stored images can be scaled-up or scaled-down for display on the TV using bi-cubic scaling. If the resulting image is not scaled-up to the maximum resolution defined by the TV standard, the image is automatically centered and bordered with a programmable border color. A 3x3 pixel filter and programmable chrominance / luminance filters are provided to generate a high quality TV image. CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13771 Technical CPU Independent Evaluation Boards Royalty Free source level Documentation Software Utilities driver code Japan North America Taiwan Seiko Epson Corporation Epson Electronics America, Inc. Epson Taiwan Technology & Trading Ltd. IC International Sales Group 14F, No. 7 2580 Orchard Parkway 421-8, Hino, Hino-shi San Jose, CA 95131, USA Song Ren Road Tokyo 191-8501, Japan Tel: (408) 922-0200 Taipei 110 Tel: 042-587-5812 Tel: 02-8786-6688 Fax: (408) 922-0238 Fax: 042-587-5564