S1D13L01F00A100 Epson

S1D13L01 S1D13L01 WQVGA Graphics Controller The S1D13L01 is a simple, multi-purpose Graphics LCD Controller with 384KByte embedded SRAM display buffer which supports both RGB interface TFT panels. The S1D13L01 supports most popular CPU interfaces in both 8/16-bit and Direct/Indirect variations. The embedded display buffer allows WQVGA up to 480x272 at 24bpp or 800x480 8bpp for single layer display, or 480x272 at 16bpp (Main Layer) and 480x272 at 8bpp (PIP Layer) for two layer display. The S1D13L01s combination of multiple CPU interfaces and display interface types offers a versatile, yet easy to develop display system. Additionally, it offers Multiple Window support, Transparency and Alpha Blending functions. It is a flexible, low cost, low power, single chip solution designed to meet the demands of embedded markets such as low end IP phone devices where total system cost and battery life are major concerns. Its impartiality to CPU type or operating system also makes it an ideal display solution for a wide variety of other applications such as Office Automation, Medical instruments and Factory Automation applications. FEATURES General Purpose IO Pins 384kByte Embedded Memory Direct and Indirect CPU Interfaces LUT 256wordx24bitx3pcs for both Main and PIP 8/16-bit data bus width layer SPI CPU interface Alpha Blending, Transparency, Flashing Support for single panel implementation: Software initiated Power Save Mode - RGB Interface TFT panel H/PIOVDD: 3.3 or 1.8V, CORE/PLLVDD: 1.5V Programmable resolutions (up to 800x480 8bpp) Clocks can be selected from embedded PLL or and color depth (up to 24 bpp) digital clock inputs Multiple Window (Layer) support for Main and PIP Temperature Range: -40~ 85 Rotation (Swivel View) 90 /180 /270 Package: QFP15 128-pin, 0.4mm pin pitch SYSTEM BLOCK DIAGRAM TFT(RGB digital) Control Signals HOST S1D13L01 CPU S1D13L01 Features Embedded display buffer 2 layer support Alpha Blending and Transparency PIP layer Flashing Programmable PLL S1D13L01 DESCRIPTION CPU Interface 384KByte Embedded Memory Support for most popular CPU interfaces Maximum Resolution for WQVGA: Direct/Indirect Addressing 1 layer: 8/16-bit interface support 480x272 at 24bpp or SPI 800x480 at 8bpp 2 layer: Display Support Main 480x272 at 16bpp and Single panel implementation can be: PIP 480x272 at 8bpp RGB Interface TFT panel Programmable resolutions up to 800x480 8bpp Miscellaneous Programmable color depths up to 24 bpp Internal System Speed: 66MHz Software initiated power save mode Display Features Multiple General Purpose IO pins Multiple Window (Layer) support for Main and PIP Flexible clock structure: Alpha Blending and Transparency Embedded PLL PIP Flashing Digital clock inputs LUT 256wordx24bitx3pcs for both Main and PIP Operating Temperature Range: -40~ 85 layer Low Operating Voltage: Rotation (Swivel View) 90 /180 /270 PLL/CORE 1.5 volts and VDD PIO/HIO 3.3 or 1.8 volts VDD Package: QFP15 128-pin, 0.4mm pin pitch NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.