S1D13L03 S1D13L03 WVGA Graphics Controller The S1D13L03 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13L03 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates. Resolutions supported include 800x480 single buffered and 352x416 double buffered. The S1D13L03 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. FEATURES 16/18 bit-per-pixel (bpp) color depths. Embedded 768K byte SRAM Display Buffer Low Operating Voltage Double-Buffer available to prevent image tearing during 8/16-bit Intel 80 interface (used for display or register streaming input data). Internal programmable PLL. RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or Single MHz clock input: CLKI. 18 bpp). General Purpose Input/Output pins. Active Matrix TFT interface - 18-bit interface. Supports resolutions up to 800x480. Hardware / Software Power Save mode. SYSTEM BLOCK DIAGRAM TFT(RGB digital) Control Signals HOST S1D13L03 CPU S1D13L03 Features 768kB SRAM Gamma LUT 18-bit TFT interface S1D13L03 DESCRIPTION Digital Video Integrated Frame Buffer RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). Embedded 768K byte SRAM display buffer. Display Features CPU Interface 16/18 bit-per-pixel (bpp) color depths. 8/16-bit Intel 80 interface (used for display or register data). 16 bpp to 18 bpp Input Data conversion. Chip select is used to select device. When inactive, any All display writes are handled by window apertures/position input data/command will be ignored. for complete or partial display updates. All window coordinates are referenced to top left corner of the displayed image. Panel Support Double-Buffer available to prevent image tearing during Active Matrix TFT interface. streaming input. Resolutions supported must fit inside 384k 18-bit interface. bytes (1/2 of total available display buffer). Typical resolution Supports resolutions up to 800x480. of 352x416. Miscellaneous Internal programmable PLL. Single MHz clock input: CLKI. CLKI available as CLKOUT (separate CLKOUTEN pin associated with output). Hardware / Software Power Save mode. Input pin to Enable/Disable Power Save Mode. General Purpose Input/Output pins are available (GPIO 7:0 ). COREVDD 1.5 volts and IOVDD 1.65 ~ 3.6 volts QFP21 176-pin package NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies. EPSON semiconductor website