GRAPHICS
S1D13781
S1D13781 WQVGA Graphics Controller August 2009
The S1D13781 is a simple, multi-purpose Graphics LCD Controller with 384KByte embedded SRAM display
buffer which supports both RGB interface TFT and CSTN panels. The S1D13781 supports most popular CPU
interfaces in both 8/16-bit and Direct/Indirect variations. The embedded display buffer allows WQVGA up to
480x272 at 24bpp or 800x480 8bpp for single layer display, or 480x272 at 16bpp (Main Layer) and 480x272 at
8bpp (PIP Layer) for two layer display.
The S1D13781s combination of multiple CPU interfaces and display interface types offers a versatile, yet easy to
develop display system. Additionally, it offers Multiple Window support, Transparency and Alpha Blending
functions, as well as 2D BitBLT functions. It is a flexible, low cost, low power, single chip solution designed to meet
the demands of embedded markets such as low end IP phone devices where total system cost and battery life
are major concerns. Its impartiality to CPU type or operating system also makes it an ideal display solution for a
wide variety of other applications such as Office Automation and Factory Automation applications.
n FEATURES
384KByte Embedded Memory General Purpose IO Pins
Direct and Indirect CPU Interfaces LUT 256wordx24bitx3pcs for both Main and PIP
8/16-bit data bus width layer
SPI CPU interface Alpha Blending, Transparency, Flashing
Support for single panel implementation: 2D BitBLT
- RGB Interface TFT panel Software initiated Power Save Mode
- Color and Monochrome STN H/PIOVDD: 3.3 or 1.8V, CORE/PLLVDD: 1.5V
Programmable resolutions (up to 800x480@8bpp) Clocks can be selected from embedded PLL or
and color depth (up to 24 bpp) digital clock inputs
Multiple Window (Layer) support for Main and PIP Temperature Range: -40 ~ 85
Rotation (Swivel View) 90/180/270 Package: QFP100-pin, 0.5mm pin pitch
n SYSTEM BLOCK DIAGRAM
TFT, CSTN
Control Signals
Host S1D13781
CPU
S1D13781 Features
Embedded display buffer
2 layer support
Alpha Blending and Transparency
PIP layer Flashing
Programmable PLL
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S1D13781
n DESCRIPTION
CPU Interface 384KByte Embedded Memory
Support for most popular CPU interfaces Maximum Resolution for WQVGA:
Direct/Indirect Addressing 1 layer: 480x272 at 24bpp or
8/16-bit interface support 800x480 at 8bpp
SPI 2 layer: Main 480x272 at 16bpp and
PIP 480x272 at 8bpp
Display Support
Miscellaneous
Single panel implementation can be:
RGB Interface TFT panel 2D BitBLT
Color and Monochrome STN Internal System Speed: TBD
Programmable resolutions up to 800x480@8bpp Software initiated power save mode
Programmable color depths up to 24 bpp Multiple General Purpose IO pins
Flexible clock structure:
Display Features
Embedded PLL
Multiple Window (Layer) support for Main and PIP Digital clock inputs
Alpha Blending and Transparency Operating Temperature Range: -40 ~ 85
PIP Flashing Low Operating Voltage:
LUT 256wordx24bitx3pcs for both Main and PIP PLL/CORE 1.5 volts and
VDD
layer PIO/HIO 3.3 or 1.8 volts
VDD
Rotation (Swivel View) 90/180/270 Package: QFP 100-pin, 0.5mm pin pitch
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS
S1D13781 Technical CPU Independent S1D13781 Evaluation Royalty Free source level
Documentation Software Utilities Boards driver code
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