AFBR-79E3PZ AFBR-79E3PZ QSFP+ 3SR4 Pluggable, Parallel Fiber-Optics Module for 40 Gb and 10 Gb Ethernet Applications Data Sheet Description Features An alternative solution of IEEE 802.3ba 40GBASE-LR4 The Avago Technologies AFBR-79E3PZ is a Four-Channel, modules to extend the support of MMF reach with low Pluggable, Parallel, Fiber-Optic QSFP+ Transceiver with power and low cost in the data center applications integrated pull tab for 40 Gigabit Ethernet (40GbE) appli- cations with extended reach up to 300 m (400 m) using Compliant to the 40GbE IEEE 802.3ba-2010 OM3 (OM4) multimode fiber (MMF) and with added capa - specifications (40GBASE-SR4 and XLPPI) and per bility of inter-operating with IEEE 10GBASE-SR compliant channel basis to the IEEE 802.3ae 10GBASE-SR optical products that can manage higher incoming optical power. specification with extended mean laser optical power This transceiver is a high performance module for short- Fiber links to a QSFP+ 3SR4 and eSR4 module and range multi-lane data communication and interconnect QSFP+3SR4 up to 300 m (400 m) using OM3 (OM4) applications. It integrates four data lanes in each direction MMF, and to a QSFP+ SR4 module up to 100 m (150 m) with each lane operating at 10.3125 Gbps, giving an ag- using OM3 (OM4) MMF gregated bandwidth of 40 Gbps. This transceiver can also Support optical interoperability up to 300 m (400 m) be used for high density 10 Gigabit Ethernet applications. using OM3 (OM4) MMF with IEEE 802.3ae 10GBASE-SR It allows optical interoperability up to 300 m (400 m) using compliant modules that can manage receiving optical OM3 (OM4) MMF with any 10 Gigabit Ethernet (10GbE) power up to +1 dBm transceivers, compliant to the IEEE 802.3ae 10GBASE-SR Compliant to industry-standard QSFP+ SFF-8436 specifications with a minimum 1 dBm of receiver overload. Specification Revision 4.1 It provides an effective port count of over 100 within 1 RU rack. The pull tab facilitates the insertion and extraction Power Level 1: Max Power < 1.5 W of these transceivers in such high density environment. High port density: 21 mm horizontal port pitch This transceiver is designated as a QSFP+ 3SR4 solution, Pull tab: ease of transceiver insertion and extraction where the digit3 represents 300 m link distance using tab color codedOrang for 3SR4 identification OM3 MMF. Operates at 10.3125 Gbps per channel with 64b/66b These modules are designed to operate over multimode encoded data fiber systems using a nominal wavelength of 850 nm. The 0 to 70C case temperature operating range electrical interface uses a 38 contact edge type connector. Proven High Reliability 850 nm technology: Avago The optical interface uses an 8 or 12 fiber MTP (MPO) VCSEL array transmitter and Avago PIN array receiver connector. This module incorporates Avago Technolo- gies proven integrated circuit and VCSEL technology to Hot pluggable transceiver for servicing and ease of provide reliable long life, high performance, and consis- installation tent service. Two Wire Serial (TWS) interface with Digital Monitoring and maskable interrupts for expanded functionality Part Number Ordering Options Utilizes a standard 12/8 lane optical fiber with MTP AFBR-79E3PZ QSFP+ 3SR4 with full real-time digital (MPO) optical connector for high density and thin, diagnostic monitoring light-weight cable management. AFBR-79Q4EKZ* Evaluation Board AFBR-79Q2EKZ** Evaluation Kit Applications 40GbE and high density 10GbE interconnects * Includes GUI and User Guide ** Includes GUI, User Guide, i-Port and Power Supply Datacom/Telecom switch & router connections Data aggregation and backplane applications Proprietary protocol and density applications Patent - www.avagotech.com/patents Avago Technologies ConfidentialOptical Interface 1x4 VCSEL Array 1x4 PIN Array Electrical Interface Transmitter Receiver The optical transmitter portion of the transceiver (see The optical receiver portion of the transceiver (see Figure 1) incorporates a 4-channel VCSEL (Vertical Cavity Figure 1) incorporates a 4-channel PIN photodiode array, a Surface Emitting Laser) array, a 4-channel input buffer and 4-channel TIA array, a 4 channel output buffer, diagnostic laser driver, diagnostic monitors, control and bias blocks. monitors, and control and bias blocks. The Rx Output The transmitter is designed for EN 60825 and CDRH eye Buffer provides CML compatible differential outputs for safety compliance Class 1 out of the module. The Tx the high speed electrical interface presenting nominal sin- Input Buffer provides CML compatible differential inputs gle-ended output impedances of 50 Ohms to AC ground presenting a nominal differential input impedance of and 100 Ohms differentially that should be differentially 100 Ohms. AC coupling capacitors are located inside the terminated with 100 Ohms. AC coupling capacitors are QSFP+ module and are not required on the host board. For located inside the QSFP+ module and are not required module control and interrogation, the control interface on the host board. Diagnostic monitors for optical input (LVTTL compatible) incorporates a Two Wire Serial (TWS) power are implemen-ted and results are available through interface of clock and data signals. Diagnostic monitors the TWS interface. for VCSEL bias, module temperature, and module power Alarm and warning thresholds are established for the supply voltage are implemented and results are available monitored attributes. Flags are set and interrupts gene- through the TWS interface. rated when the attributes are outside the thresholds. Flags Alarm and warning thresholds are established for are also set and interrupts generated for loss of optical the monitored attributes. Flags are set and interrupts input signal (LOS). All flags are latched and will remain generated when the attributes are outside the thresholds. set even if the condition initiating the flag clears and Flags are also set and interrupts generated for loss of input operation resumes. All interrupts can be masked and flags signal (LOS) and transmitter fault conditions. All flags are are reset upon reading the appropriate flag register. The latched and will remain set even if the condition initiating electrical output will squelch for loss of input signal (unless the latch clears and operation resumes. All interrupts can squelch is disabled) and channel de-activation through be masked and flags are reset by reading the appropriate TWS interface. Status and alarm/warning information are flag register. The optical output will squelch for loss of available via the TWS interface. To reduce the need for input signal unless squelch is disabled. Fault detection polling, the hardware interrupt signal is provided to inform or channel deactivation through the TWS interface will hosts of an assertion of alarm, warning and/or LOS. disable the channel. Status, alarm/warning and fault infor- mation are available via the TWS interface. To reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of alarm, warning, LOS and/ or Tx fault. TX Input Bu er Laser Driver Din 4:1 p/n (8) 4 Channels 4 Channels SCL SDA ModSelL Diagnostic Control LPMode Monitors ModPresL ResetL IntL RX Output Bu er TIA Dout 4:1 p/n (8) 4 Channels 4 Channels Figure 1. Transceiver Block Diagram 2 Avago Technologies Confidential