AFBR-79EEPZ QSFP+ eSR4 Pluggable, Parallel Fiber-Optics Module for 40 Gb and 10 Gb Ethernet Applications Data Sheet Description Features An alternative solution of IEEE 802.3ba 40GBASE-LR4 The Avago Technologies AFBR-79EEPZ is a Four-Channel, modules to extend the support of MMF reach with low Pluggable, Parallel, Fiber-Optic QSFP+ Transceiver with in- power and low cost in the data center applications tegrated push-pull tab for 40 Gigabit Ethernet (40GbE) ap- plications with extended reach up to 300m (400m) using Compliant to the 40GbE IEEE 802.3ba-2010 OM3 (OM4) multimode fiber (MMF) and with added capa - specifications (40GBASE-SR4 and XLPPI) and per bility of inter-operating with IEEE 10GBASE-SR compliant channel basis to the IEEE 802.3ae 10GBASE-SR optical products. This transceiver is a high performance module specification for short-range multi-lane data communication and in- Fiber links to a QSFP+ eSR4 module up to 300m (400m) terconnect applications. It integrates four data lanes using OM3 (OM4) MMF, and to a QSFP+ SR4 module up in each direction with each lane operating at 10.3125 to 100m (150m) using OM3 (OM4) MMF Gbps, giving an aggregated bandwidth of 40 Gbps. This Support optical interoperability up to 300m (400m) transceiver can also be used for high density 10 gigabit using OM3 (OM4) MMF with IEEE 802.3ae 10GBASE- Ethernet applications. It allows optical interoperability SR compliant modules of various form factors such as up to 300m (400m) using OM3 (OM4) MMF with any 10 SFP+, XFP and X2 gigabit Ethernet (10GbE) transceivers, compliant to the Compliant to industry-standard QSFP+ SFF-8436 IEEE 802.3ae 10GBASE-SR specifications, of form factors Specification Revision 4.1 such as SFP+, XFP and X2. It provides an effective port count of over 100 within 1 RU rack. The push-pull tab fa- Power Level 1: Max Power < 1.5W cilitates the insertion and extraction of these transceiv- High port density: 21mm horizontal port pitch ers in such high density environment. This transceiver Push-pull tab: ease of transceiver insertion and is designated as a QSFP+ eSR4 solution, where the letter extraction tab front clip color codedOrang for eSR4 represents extended reach beyond 100m MMF with identification interoperability between this QSFP+ transceiver and any Operates at 10.3125 Gbps per channel with 64b/66b IEEE 10GBASE-SR compliant modules. encoded data These modules are designed to operate over multimode 0 to 70C case temperature operating range fiber systems using a nominal wavelength of 850nm. The Proven High Reliability 850 nm technology: Avago electrical interface uses a 38 contact edge type connector. VCSEL array transmitter and Avago PIN array receiver The optical interface uses an 8 or 12 fiber MTP (MPO) connector. This module incorporates Avago Technolo- Hot pluggable transceiver for servicing and ease of gies proven integrated circuit and VCSEL technology to installation provide reliable long life, high performance, and consis- Two Wire Serial (TWS) interface with Digital Monitoring tent service. and maskable interrupts for expanded functionality Part Number Ordering Options Utilizes a standard 12/8 lane optical fiber with MTP (MPO) optical connector for high density and thin, AFBR-79EEPZ QSFP+ eSR4 with full real-time digital light-weight cable management. diagnostic monitoring and push-pull tab AFBR-79Q4EKZ* Evaluation Board Applications AFBR-79Q2EKZ** Evaluation Kit 40GbE and high density 10GbE interconnects * Includes GUI and User Guide Datacom/Telecom switch & router connections ** Includes GUI, User Guide, i-Port and Power Supply Data aggregation and backplane applications Proprietary protocol and density applications Patent - www.avagotech.com/patents Avago Technologies ConfidentialOptical Interface 1x4 VCSEL Array 1x4 PIN Array Electrical Interface Transmitter Receiver The optical transmitter portion of the transceiver (see The optical receiver portion of the transceiver (see Figure 1) incorporates a 4-channel VCSEL (Vertical Cavity Figure 1) incorporates a 4-channel PIN photodiode array, a Surface Emitting Laser) array, a 4-channel input buffer and 4-channel TIA array, a 4 channel output buffer, diagnostic laser driver, diagnostic monitors, control and bias blocks. monitors, and control and bias blocks. The Rx Output The transmitter is designed for EN 60825 and CDRH eye Buffer provides CML compatible differential outputs for safety compliance Class 1 out of the module. The Tx the high speed electrical interface presenting nominal sin- Input Buffer provides CML compatible differential inputs gle-ended output impedances of 50 Ohms to AC ground presenting a nominal differential input impedance of and 100 Ohms differentially that should be differentially 100 Ohms. AC coupling capacitors are located inside the terminated with 100 Ohms. AC coupling capacitors are QSFP+ module and are not required on the host board. For located inside the QSFP+ module and are not required module control and interrogation, the control interface on the host board. Diagnostic monitors for optical input (LVTTL compatible) incorporates a Two Wire Serial (TWS) power are implemen-ted and results are available through interface of clock and data signals. Diagnostic monitors the TWS interface. for VCSEL bias, module temperature, and module power Alarm and warning thresholds are established for the supply voltage are implemented and results are available monitored attributes. Flags are set and interrupts gene- through the TWS interface. rated when the attributes are outside the thresholds. Flags Alarm and warning thresholds are established for are also set and interrupts generated for loss of optical the monitored attributes. Flags are set and interrupts input signal (LOS). All flags are latched and will remain generated when the attributes are outside the thresholds. set even if the condition initiating the flag clears and Flags are also set and interrupts generated for loss of input operation resumes. All interrupts can be masked and flags signal (LOS) and transmitter fault conditions. All flags are are reset upon reading the appropriate flag register. The latched and will remain set even if the condition initiating electrical output will squelch for loss of input signal (unless the latch clears and operation resumes. All interrupts can squelch is disabled) and channel de-activation through be masked and flags are reset by reading the appropriate TWS interface. Status and alarm/warning information are flag register. The optical output will squelch for loss of available via the TWS interface. To reduce the need for input signal unless squelch is disabled. Fault detection polling, the hardware interrupt signal is provided to inform or channel deactivation through the TWS interface will hosts of an assertion of alarm, warning and/or LOS. disable the channel. Status, alarm/warning and fault infor- mation are available via the TWS interface. To reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of alarm, warning, LOS and/ or Tx fault. TX Input Bu er Laser Driver Din 4:1 p/n (8) 4 Channels 4 Channels SCL SDA ModSelL Diagnostic Control LPMode Monitors ModPresL ResetL IntL RX Output Bu er TIA Dout 4:1 p/n (8) 4 Channels 4 Channels Figure 1. Transceiver Block Diagram 2 Avago Technologies Confidential