AFBR-79EIDZ
QSFP+ iSR4 Pluggable, Parallel Fiber-Optics Module
for 40Gb Ethernet, 4 x 10Gb Ethernet
and InfiniBand Applications
Data Sheet
Description Features
The Avago Technologies AFBR-79EIDZ is a Four-Channel, Compliant to the 40GBASE-SR4 and XLPPI Specifications
Pluggable, Parallel, Fiber-Optic QSFP+ Transceiver for 40 per IEEE 802.3ba-2010
Gigabit Ethernet (40GbE) applications with added capa-
Support optical interoperability with IEEE 802.3ae
bility of inter-operating with IEEE 10GBASE-SR compliant
10GBASE-SR modules of various form factors such as
products. It also supports 4 x 10G InfiniBand (IB) quadruple
SFP+, XFP, and X2
data rate (40G-IB-QDR) application and is backward com-
Support 40G-IB-QDR / 20G-IB-DDR / 10G-IB-SDR
patible to the 4 x 5G IB dual data rate (20G-IB-DDR) and 4
applications
x 2.5G IB single data rate (10G-IB-SDR) applications. This
transceiver is a high performance module for short-range Compliant to the industry standard SFF-8436 QSFP+
multi-lane data communication and interconnect ap- Specification Revision 3.5
plications. It integrates four data lanes in each direction
Power Level 1: Max Power <1.5W
with each lane operating at 10.3125 Gbps, giving an ag-
High port density: 21mm horizontal port pitch
gregated bandwidth of 40 Gbps. This transceiver can
also be used for high density 10 Gigabit Ethernet appli- Operates at 10.3125 Gbps per channel with 64b/66b
cation to allow effective port count of over 100 within encoded data for 40GbE / 10GbE applications and at
1 RU rack. It allows optical interoperability with any 10 10 Gbps with 8b/10b compatible encoded data for
Gigabit Ethernet (10GbE) transceiver, compliant to the 40G-IB-QDR application
IEEE 802.3ae 10GBASE-SR specifications, of form factors
Links up to 100m using OM3 fiber and 150m using
such as SFP+, XFP and X2. This transceiver is designated
OM4 fiber
as a QSFP+ iSR4 solution, where the letter i represents in-
0 to 70C case temperature operating range
teroperability between this QSFP+ transceiver with any
10GBASE-SR compliant modules. Proven High Reliability 850 nm technology: Avago
VCSEL array transmitter and Avago PIN array receiver
This QSFP+ transceiver link length for either 40 Gigabit
Hot pluggable transceiver for servicing and ease of
Ethernet or high density 10 Gigabit Ethernet application
installation
is up to 100 m using OM3 fiber or 150 m using OM4 fiber.
These modules are designed to operate over multimode
Two Wire Serial (TWS) interface with maskable
fiber systems using a nominal wavelength of 850nm. The
interrupts for expanded functionality
electrical interface uses a 38 contact edge type connector.
Utilizes a standard 12/8 lane optical fiber with MTP
The optical interface uses an 8 or 12 fiber MTP (MPO)
(MPO) optical connector for high density and thin,
connector. This module incorporates Avago Technolo-
light-weight cable management
gies proven integrated circuit and VCSEL technology to
provide reliable long life, high performance, and consis-
Applications
tent service.
40GbE, high density 4 x 10GbE, and 40G-IB-QDR /
Part Number Ordering Options
20G-IB-DDR / 10G-IB-SDR interconnects
AFBR-79EIDZ QSFP+ iSR4 module with full real-time
Datacom/Telecom switch & router connections
digital diagnostic monitoring
Data aggregation and backplane applications
AFBR-79Q4EKZ* Evaluation Board
Proprietary protocol and density applications
AFBR-79Q2EKZ** Evaluation Kit
* Includes GUI and User Guide
** Includes GUI, User Guide, i-Port and Power Supply
Patent - www.avagotech.com/patents Optical Interface
1x4 VCSEL Array 1x4 PIN Array
Electrical Interface
Receiver
Transmitter
The optical receiver portion of the transceiver (see
The optical transmitter portion of the transceiver (see
Figure 1) incorporates a 4-channel PIN photodiode array, a
Figure 1) incorporates a 4-channel VCSEL (Vertical Cavity
4-channel TIA array, a 4 channel output buffer, diagnostic
Surface Emitting Laser) array, a 4-channel input buffer and
monitors, and control and bias blocks. The Rx Output
laser driver, diagnostic monitors, control and bias blocks.
Buffer provides CML compatible differential outputs for
The transmitter is designed for EN 60825 and CDRH eye
the high speed electrical interface presenting nominal sin-
safety compliance; Class 1 out of the module. The Tx
gle-ended output impedances of 50 Ohms to AC ground
Input Buffer provides CML compatible differential inputs
and 100 Ohms differentially that should be differentially
presenting a nominal differential input impedance of
terminated with 100 Ohms. AC coupling capacitors are
100 Ohms. AC coupling capacitors are located inside the
located inside the QSFP+ module and are not required
QSFP+ module and are not required on the host board. For
on the host board. Diagnostic monitors for optical input
module control and interrogation, the control interface
power are implemen-ted and results are available through
(LVTTL compatible) incorporates a Two Wire Serial (TWS)
the TWS interface.
interface of clock and data signals. Diagnostic monitors
for VCSEL bias, module temperature, and module power
Alarm and warning thresholds are established for the
supply voltage are implemented and results are available
monitored attributes. Flags are set and interrupts gene-
through the TWS interface.
rated when the attributes are outside the thresholds. Flags
are also set and interrupts generated for loss of optical
Alarm and warning thresholds are established for
input signal (LOS). All flags are latched and will remain
the monitored attributes. Flags are set and interrupts
set even if the condition initiating the flag clears and
generated when the attributes are outside the thresholds.
operation resumes. All interrupts can be masked and flags
Flags are also set and interrupts generated for loss of input
are reset upon reading the appropriate flag register. The
signal (LOS) and transmitter fault conditions. All flags are
electrical output will squelch for loss of input signal (unless
latched and will remain set even if the condition initiating
squelch is disabled) and channel de-activation through
the latch clears and operation resumes. All interrupts can
TWS interface. Status and alarm/warning information are
be masked and flags are reset by reading the appropriate
available via the TWS interface. To reduce the need for
flag register. The optical output will squelch for loss of
polling, the hardware interrupt signal is provided to inform
input signal unless squelch is disabled. Fault detection
hosts of an assertion of alarm, warning and/or LOS.
or channel deactivation through the TWS interface will
disable the channel. Status, alarm/warning and fault infor-
mation are available via the TWS interface. To reduce the
need for polling, the hardware interrupt signal is provided
to inform hosts of an assertion of alarm, warning, LOS and/
or Tx fault.
TX Input Bu er Laser Driver
Din[4:1][p/n] (8)
4 Channels 4 Channels
SCL
SDA
ModSelL
Diagnostic
Control
LPMode
Monitors
ModPresL
ResetL
IntL
RX Output Bu er TIA
Dout[4:1][p/n] (8)
4 Channels 4 Channels
Figure 1. Transceiver Block Diagram
2