FUJITSU SEMICONDUCTOR DS706-00028-0v01-E DATA SHEET TM TM 32-bit ARM Cortex -M3 based Microcontroller MB9B110R Series MB9BF112N/R, MB9BF114N/R, MB9BF115N/R, MB9BF116N/R DESCRIPTION The MB9B110R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces ( UART, CSIO, 2 I C, LIN). The products which are described in this data sheet are placed into TYPE4 product categories inFM3 MB9Axxx/MB9Bxxx Series PERIPHERAL MANUA. Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries. Copyright2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2012.1 FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0 MB9B110R Series FEATURES 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 144MHz Frequency Operation Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories Flash memory These series are based on two independent on-chip Flash memories. MainFlash Up to 512Kbyte Built-in Flash Accelerator System with 16Kbyte trace buffer memory The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72MHz. Even at the operation frequency more than 72MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. Security function for code protection WorkFlash 32Kbyte Read cycle 4wait-cycle: the operation frequency more than 72MHz 2wait-cycle: the operation frequency more than 40MHz, and to 72MHz 0wait-cycle: the operation frequency to 40MHz Security function is shared with code protection SRAM This Series contain a total of up to 64Kbyte on-chip SRAM memories. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 32 Kbyte SRAM1: Up to 32 Kbyte External Bus Interface Supports SRAM, NOR and NAND Flash device Up to 8 chip selects 8/16-bit Data width Up to 25-bit Address bit Supports Address/Data multiplex Supports external RDY input 2 DS706-00028-0v01-E FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0