HT9170D-18SOPLF Holtek

HT9170B/HT9170D DTMFReceiver Features Operating voltage: 2.5V~5.5V Tristate data output for MCU interface Minimal external components 3.58MHz crystal or ceramic resonator No external filter is required 1633Hz can be inhibited by the INH pin Low standby current (on power down mode) HT9170B: 18-pin DIP package HT9170D: 18-pin SOP package Excellent performance General Description The HT9170B/D are Dual Tone Multi Frequency (DTMF) Highly accurate switched capacitor filters are imple- receivers integrated with digital decoder and bandsplit mented to divide tone signals into low and high group filter functions as well as power-down mode and inhibit signals. A built-in dial tone rejection circuit is provided to mode operations. Such devices use digital counting eliminate the need for pre-filtering. techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output. Selection Table Function Operating OSC Tristate Power 1633Hz DV DVB Package Voltage Frequency Data Output Down Inhibit Part No. HT9170B 2.5V~5.5V 3.58MHz 18 DIP HT9170D 2.5V~5.5V 3.58MHz 18 SOP Block Diagram 4 * ( * - / . / 0 1 0 . & 0 * - & * 2 % * ) + , * * * ( - % * & 3 ( . Rev. 1.11 1 February 23, 2009HT9170B/HT9170D Pin Assignment * * * * ( 5 / 0 1 0 ( / 0 1 0 5 & . & 0 & 6 6 . & 0 / . * / . * 7 7 3 ( * 3 ( 7 7 * 4 * ( 6 * 4 * ( * 6 * 5 5 * * 2 * 2 & & . & & 8 2 8 2 . Pin Description Internal Pin Name I/O Description Connection Operational VP I Operational amplifier non-inverting input Amplifier VN I Operational amplifier inverting input GS O Operational amplifier output terminal VREEF O VREF Reference voltage output, normally V /2 DD X1 I The system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip. oscillator A standard 3.579545MHz crystal connected to X1 and X2 terminals imple- X2 O ments the oscillator function. CMOS IN Active high. This enables the device to go into power down mode and inhibits PWDN I Pull-low the oscillator. This pin input is internally pulled down. CMOS IN Logic high. This inhibits the detection of tones representing characters A, B, C INH I Pull-low and D. This pin input is internally pulled down. VSS Negative power supply, ground CMOS IN OE I D0~D3 output enable, high active Pull-high Receiving data output terminals CMOS OUT D0~D3 O OE= H : Output enable Tristate OE= L : High impedance Data valid output DV O CMOS OUT When the chip receives a valid tone (DTMF) signal, the DV goes high other- wise it remains low. EST O CMOS OUT Early steering output (see Functional Description) Tone acquisition time and release time can be set through connection with ex- RT/GT I/O CMOS IN/OUT ternal resistor and capacitor. VDD Positive power supply, 2.5V~5.5V for normal operation Rev. 1.11 2 February 23, 2009