MAX 10 FPGA Device Overview
2015.11.02
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MAX 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate
the optimal set of system components.
The highlights of the MAX 10 devices include:
Internally stored dual configuration flash
User flash memory
Instant on support
Integrated analog-to-digital converters (ADCs)
Single-chip Nios II soft core processor support
MAX 10 devices are the ideal solution for system management, I/O expansion, communication control
planes, industrial, automotive, and consumer applications.
Related Information
MAX 10 FPGA Device Datasheet
Key Advantages of MAX 10 Devices
Table 1: Key Advantages of MAX 10 Devices
Advantage Supporting Feature
Simple and fast configuration Secure on-die flash memory enables device configuration in
less than 10 ms
Flexibility and integration
Single device integrating PLD logic, RAM, flash memory,
digital signal processing (DSP), ADC, phase-locked loop
(PLL), and I/Os
Small packages available from 3 mm 3 mm
Low power
Sleep modesignificant standby power reduction and
resumption in less than 1 ms
Longer battery liferesumption from full power-off in
less than 10 ms
20-year-estimated life cycle Built on TSMC's 55 nm embedded flash process technology
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Summary of MAX 10 Device Features
2015.11.02
Advantage Supporting Feature
High productivity design tools
Quartus Prime web edition (no cost license)
Qsys system integration tool
Digital Signal Processing (DSP) Builder
Nios II Embedded Design Suite (EDS)
Summary of MAX 10 Device Features
Table 2: Summary of Features for MAX 10 Devices
Feature Description
Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process
technology
Packaging
Low cost, small form factor packagessupport multiple
packaging technologies and pin pitches
Multiple device densities with compatible package footprints
for seamless migration between different device densities
RoHS6-compliant
Core architecture
4-input look-up table (LUT) and single register logic element
(LE)
LEs arranged in logic array block (LAB)
Embedded RAM and user flash memory
Clocks and PLLs
Embedded multiplier blocks
General purpose I/Os
Internal memory blocks
M9K9 kilobits (Kb) memory blocks
Cascadable blocks to create RAM, dual port, and FIFO
functions
User flash memory (UFM)
User accessible non-volatile storage
High speed operating frequency
Large memory size
High data retention
Multiple interface option
Embedded multiplier blocks
One 18 18 or two 9 9 multiplier modes
Cascadable blocks enabling creation of filters, arithmetic
functions, and image processing pipelines
MAX 10 FPGA Device Overview
Altera Corporation
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