Arria V Device Overview 2015.12.21 Send Feedback AV-51001 Subscribe The Arria V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid- range FPGA bandwidth 12.5 Gbps transceivers. The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (DSP) applications. Related Information Arria V Device Handbook: Known Issues Lists the planned updates to the Arria V Device Handbook chapters. Key Advantages of Arria V Devices Table 1: Key Advantages of the Arria V Device Family Advantage Supporting Feature Lowest static power in its Built on TSMC s 28 nm process technology and includes an abundance of class hard intellectual property (IP) blocks Power-optimized MultiTrack routing and core architecture Up to 50% lower power consumption than the previous generation device Lowest power transceivers of any midrange family Improved logic integration 8-input adaptive logic module (ALM) and differentiation capabil Up to 38.38 megabits (Mb) of embedded memory ities Variable-precision digital signal processing (DSP) blocks Increased bandwidth Serial data rates up to 12.5 Gbps capacity Hard memory controllers Hard processor system Tight integration of a dual-core ARM Cortex-A9 MPCore processor, (HPS) with integrated hard IP, and an FPGA in a single Arria V system-on-a-chip (SoC) ARM Cortex -A9 Supports over 128 Gbps peak bandwidth with integrated data coherency MPCore processor between the processor and the FPGA fabric 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as ISO trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance 9001:2008 of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any Registered products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134AV-51001 2 Summary of Arria V Features 2015.12.21 Advantage Supporting Feature Lowest system cost Requires as few as four power supplies to operate Available in thermal composite flip chip ball-grid array (BGA) packaging Includes innovative features such as Configuration via Protocol (CvP), partial reconfiguration, and design security Summary of Arria V Features Table 2: Summary of Features for Arria V Devices Feature Description Technology TSMC s 28-nm process technology: Arria V GX, GT, SX, and ST28-nm low power (28LP) process Arria V GZ28-nm high performance (28HP) process Lowest static power in its class (less than 1.2 W for 500K logic elements (LEs) at 85C junction under typical conditions) 0.85 V, 1.1 V, or 1.15 V core nominal voltage Packaging Thermal composite flip chip BGA packaging Multiple device densities with identical package footprints for seamless migration between different device densities (1) Leaded , lead-free (Pb-free), and RoHS-compliant options High-performance Enhanced 8-input ALM with four registers FPGA fabric Improved routing architecture to reduce congestion and improve compilation time Internal memory M10K10-kilobits (Kb) memory blocks with soft error correction code (ECC) blocks ( Arria V GX, GT, SX, and ST devices only) M20K20-Kb memory blocks with hard ECC ( Arria V GZ devices only) Memory logic array block (MLAB)-640-bit distributed LUTRAM where you can use up to 50% of the ALMs as MLAB memory (1) Contact Altera for availability. Arria V Device Overview Altera Corporation Send Feedback