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Virtex-6 Family Overview
DS150 (v2.5) August 20, 2015 Product Specification
General Description
Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware
components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL
(Advanced Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct sub-families. This overview
covers the devices in the LXT, SXT, and HXT sub-families. Each sub-family contains a different ratio of features to most efficiently address
the needs of a wide variety of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-
in system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGA-
based systems. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 FPGAs are a programmable alternative to custom
ASIC technology. Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance
DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft
microprocessor capabilities.
Summary of Virtex-6 FPGA Features
Three sub-families: Advanced DSP48E1 slices
Virtex-6 LXT FPGAs: High-performance logic with 25 x 18, two's complement multiplier/accumulator
advanced serial connectivity Optional pipelining
Virtex-6 SXT FPGAs: Highest signal processing New optional pre-adder to assist filtering
capability with advanced serial connectivity applications
Virtex-6 HXT FPGAs: Highest bandwidth serial Optional bitwise logic functionality
connectivity Dedicated cascade connections
Compatibility across sub-families Flexible configuration options
LXT and SXT devices are footprint compatible in SPI and Parallel Flash interface
the same package
Multi-bitstream support with dedicated fallback
Advanced, high-performance FPGA Logic
reconfiguration logic
Real 6-input look-up table (LUT) technology Automatic bus width detection
Dual LUT5 (5-input LUT) option
System Monitor capability on all devices
LUT/dual flip-flop pair for applications requiring rich
On-chip/off-chip thermal and supply voltage
register mix
monitoring
Improved routing efficiency
JTAG access to all monitored quantities
64-bit (or two 32-bit) distributed LUT RAM option
Integrated interface blocks for PCI Express designs
per 6-input LUT
Compliant to the PCI Express Base Specification
SRL32/dual SRL16 with registered outputs option
2.0
Powerful mixed-mode clock managers (MMCM)
Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with
MMCM blocks provide zero-delay buffering,
GTX transceivers
frequency synthesis, clock-phase shifting, input-
Endpoint and Root Port capable
jitter filtering, and phase-matched clock division
x1, x2, x4, or x8 lane support per block
36-Kb block RAM/FIFOs
GTX transceivers: up to 6.6 Gb/s
Dual-port RAM blocks
Data rates below 480 Mb/s supported by
Programmable
oversampling in FPGA logic.
- Dual-port widths up to 36 bits
GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s
- Simple dual-port widths up to 72 bits
Enhanced programmable FIFO logic Integrated 10/100/1000 Mb/s Ethernet MAC block
Built-in optional error-correction circuitry
Supports 1000BASE-X PCS/PMA and SGMII
Optionally use each block as two independent
using GTX transceivers
18 Kb blocks
Supports MII, GMII, and RGMII using SelectIO
High-performance parallel SelectIO technology
technology resources
1.2 to 2.5V I/O operation
2500Mb/s support available
Source-synchronous interfacing using
40 nm copper CMOS process technology
ChipSync technology
1.0V core voltage (-1, -2, -3 speed grades only)
Digitally controlled impedance (DCI) active
Lower-power 0.9V core voltage option (-1L speed
termination
Flexible fine-grained I/O banking grade only)
High-speed memory interface support with
High signal-integrity flip-chip packaging available in
integrated write-leveling capability
standard or Pb-free package options
20092015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS150 (v2.5) August 20, 2015 www.xilinx.com
Product Specification 1Virtex-6 Family Overview
Virtex-6 FPGA Feature Summary
Table 1: Virtex-6 FPGA Feature Summary by Device
Configurable Logic Maximum
Block RAM Blocks
Blocks (CLBs) Transceivers
Interface
Total Max
Logic DSP48E1 Blocks for Ethernet
(4)
Device MMCMs I/O User
(2) (6)
Cells Slices PCI MACs
Max (7) (8)
Banks I/O
Max (5)
(1) (3)
Express
Slices Distributed 18 Kb 36 Kb GTX GTH
(Kb)
RAM (Kb)
XC6VLX75T 74,496 11,640 1,045 288 312 156 5,616 6 1 4 12 0 9 360
XC6VLX130T 128,000 20,000 1,740 480 528 264 9,504 10 2 4 20 0 15 600
XC6VLX195T 199,680 31,200 3,040 640 688 344 12,384 10 2 4 20 0 15 600
XC6VLX240T 241,152 37,680 3,650 768 832 416 14,976 12 2 4 24 0 18 720
XC6VLX365T 364,032 56,880 4,130 576 832 416 14,976 12 2 4 24 0 18 720
XC6VLX550T 549,888 85,920 6,200 864 1,264 632 22,752 18 2 4 36 0 30 1200
XC6VLX760 758,784 118,560 8,280 864 1,440 720 25,920 18 0 0 0 0 30 1200
XC6VSX315T 314,880 49,200 5,090 1,344 1,408 704 25,344 12 2 4 24 0 18 720
XC6VSX475T 476,160 74,400 7,640 2,016 2,128 1,064 38,304 18 2 4 36 0 21 840
XC6VHX250T 251,904 39,360 3,040 576 1,008 504 18,144 12 4 4 48 0 8 320
XC6VHX255T 253,440 39,600 3,050 576 1,032 516 18,576 12 2 2 24 24 12 480
XC6VHX380T 382,464 59,760 4,570 864 1,536 768 27,648 18 4 4 48 24 18 720
XC6VHX565T 566,784 88,560 6,370 864 1,824 912 32,832 18 4 4 48 24 18 720
Notes:
1. Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.
2. Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.
4. Each CMT contains two mixed-mode clock managers (MMCM).
5. Refer to UG517, Virtex-6 FPGA Integrated Block for PCI Express User Guide for supported core pinouts by package.
6. This table lists individual Ethernet MACs per device.
7. Does not include configuration Bank 0.
8. This number does not include GTX or GTH transceivers.
DS150 (v2.5) August 20, 2015 www.xilinx.com
Product Specification 2