DK-SI-1STX-E-A Intel

Intel Stratix 10 TX Transceiver Signal Integrity Development Kit User Guide Online Version ID: 683591 Send Feedback Version: 2019.09.27 UG-20150Contents Contents 1. Overview........................................................................................................................ 4 1.1. General Development Kit Description........................................................................4 1.2. Recommended Operating Conditions........................................................................ 5 1.3. Handling the Kit.................................................................................................... 6 2. Getting Started............................................................................................................... 7 2.1. About the Intel Quartus Prime Software..................................................................7 2.2. Development Kit Package....................................................................................... 7 2.3. Installing the Intel FPGA Download Cable II Driver.....................................................8 3. Development Kit Setup................................................................................................... 9 3.1. Setting up the Development Kit...............................................................................9 3.2. Factory Default Switch and Jumper Settings............................................................ 10 4. Development Kit Components....................................................................................... 12 4.1. Development Kit Overview.................................................................................... 12 4.2. Intel Stratix 10 TX FPGA....................................................................................... 14 4.3. MAX V CPLD........................................................................................................18 4.4. FPGA Configuration.............................................................................................. 21 4.4.1. Configuring the FPGA over Embedded Intel FPGA Download Cable II...............21 4.4.2. Configuring the FPGA through Flash Memory............................................... 22 4.4.3. Configuring the FPGA over External Intel FPGA Download Cable..................... 24 4.5. Status and Setup Elements................................................................................... 25 4.6. User Input-Output Components............................................................................. 27 4.7. Clocks................................................................................................................28 4.7.1. Transceiver Dedicated Clocks.....................................................................28 4.7.2. General-Purpose Clocks............................................................................ 29 4.7.3. Embedded Intel FPGA Download Cable II Clock............................................ 30 4.8. Transceiver Channels............................................................................................30 4.9. Communication Ports........................................................................................... 32 4.10. Flash Memory....................................................................................................33 4.10.1. Parallel NOR Flash Memory ..................................................................... 33 4.10.2. EPCQL Flash Memory..............................................................................34 4.11. System Power....................................................................................................35 4.11.1. Power Guidelines....................................................................................35 4.11.2. Power Supply.........................................................................................35 4.11.3. Power Management................................................................................ 36 4.11.4. Power Distribution System.......................................................................37 4.11.5. Thermal Limitations and Protection Guidelines............................................38 5. Board Test System........................................................................................................ 40 5.1. Preparing the Development Kit.............................................................................. 41 5.2. Running the Board Test System............................................................................. 41 5.3. Using the Board Test System.................................................................................42 5.3.1. The Configure Menu................................................................................. 42 5.3.2. The System Info Tab................................................................................ 43 5.3.3. The GPIO Tab.......................................................................................... 44 5.3.4. The EPCQ Tab..........................................................................................45 Intel Stratix 10 TX Transceiver Signal Integrity Development Kit User Send Feedback Guide 2