DK-SI-AGF014E3ES Intel

Intel Agilex F-Series Transceiver- SoC Development Kit User Guide Online Version ID: 683752 Send Feedback Version: 2021.07.27 UG-20259Contents Contents 1. Overview........................................................................................................................ 4 1.1. Block Diagram.......................................................................................................4 1.2. Feature Summary..................................................................................................5 1.3. Box Contents........................................................................................................ 5 1.4. Recommended Operating Conditions........................................................................ 5 2. Getting Started............................................................................................................... 7 2.1. Intel Quartus Prime Software and Driver Installation................................................ 7 2.2. Quick Start Guide.................................................................................................. 8 2.3. Design Examples...................................................................................................8 3. Power Up the Development Kit....................................................................................... 9 3.1. Default Settings.................................................................................................... 9 3.2. Power Up............................................................................................................10 3.3. Perform board restore.......................................................................................... 10 3.3.1. Restore board System Intel MAX 10 with default factory image...................... 10 3.3.2. Restore board QSPI flash with the default factory image................................10 3.4. Control on-board clock through Clock Controller GUI................................................ 11 3.5. Control on-board power regulator through Power Monitor GUI....................................14 4. Board Test System........................................................................................................ 19 4.1. Test the functionality of the Development Kits..........................................................19 4.1.1. The Configure Menu................................................................................. 19 4.1.2. The Sys Info Tab......................................................................................20 4.1.3. The GPIO Tab.......................................................................................... 21 4.1.4. The XCVR Tab..........................................................................................22 4.1.5. The DDR4 Tab......................................................................................... 25 4.1.6. The SSS Tab............................................................................................27 4.1.7. The EEPROM Tab......................................................................................28 5. Development Kit Hardware and Configuration.............................................................. 29 5.1. Configure FPGA and access HPS Debug Access Port by JTAG...................................... 29 5.2. Configure the FPGA device by AS modes (Default Mode)........................................... 29 5.3. Configure the FPGA device by AvST modes..............................................................29 5.4. Daughter Cards................................................................................................... 30 5.4.1. HPS Out of Box Experience (OOBE) Daughter Card.......................................30 5.4.2. HPS NAND Daughter Card......................................................................... 31 6. Custom Projects for the Development Kit..................................................................... 32 6.1. Add SmartVID settings in Intel Quartus Prime QSF file..............................................32 6.2. Golden Top......................................................................................................... 32 7. Revision History............................................................................................................33 A. Development Kit Components.......................................................................................34 A.1. System Management............................................................................................34 A.2. Power................................................................................................................ 36 A.3. Clocks................................................................................................................38 A.4. General Input/Output...........................................................................................40 Intel Agilex F-Series Transceiver-SoC Development Kit User Guide Send Feedback 2