Development Tools ACEX 1K Programmable Logic Device Family May 2003, ver. 3.4 Data Sheet Programmable logic devices (PLDs), providing low cost Features... system-on-a-programmable-chip (SOPC) integration in a single device Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions Dual-port capability with up to 16-bit width per embedded array block (EAB) Logic array for general logic functions High density 10,000 to 100,000 typical gates (see Table 1) Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity) Cost-efficient programmable architecture for high-volume 13 applications Cost-optimized process Low cost solution for high-performance communications applications System-level features TM MultiVolt I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices Low power consumption Bidirectional I/O performance (setup time t and clock-to- SU output delay t ) up to 250 MHz CO Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz Extended temperature range TM Table 1. ACEX 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000 257,000 Logic elements (LEs) 576 1,728 2,880 4,992 EABs 3 6 10 12 Total RAM bits 12,288 24,576 40,960 49,152 Maximum user I/O pins 136 171 249 333 Altera Corporation 1 DS-ACEX-3.4ACEX 1K Programmable Logic Device Family Data Sheet -1 speed grade devices are compliant with PCI Local Bus ...and More Specification, Revision 2.2 for 5.0-V operation Features Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic. Operate with a 2.5-V internal supply voltage In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port TM TM ClockLock and ClockBoost options for reduced clock delay, clock skew, and clock multiplication Built-in, low-skew clock distribution trees 100% functional testing of all devices test vectors or scan chains are not required Pull-up on I/O pins before and during configuration Flexible interconnect FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) Tri-state emulation that implements internal tri-state buses Up to six global clock signals and four global clear signals Powerful I/O pins Individual tri-state output enable control for each pin Open-drain option on each I/O pin Programmable output slew-rate control to reduce switching noise Clamp to V user-selectable on a pin-by-pin basis CCIO Supports hot-socketing 2 Altera Corporation