Stratix GX FPGA Family
December 2004, ver. 2.2 Data Sheet
The Stratix GX family of devices is Alteras second FPGA family to
Introduction
combine high-speed serial transceivers with a scalable, high-performance
logic array. Stratix GX devices include 4 to 20 high-speed transceiver
channels, each incorporating clock data recovery (CDR) technology and
embedded SERDES capability at data rates of up to 3.1875 gigabits per
second (Gbps). These transceivers are grouped by four-channel
transceiver blocks, and are designed for low power consumption and
small die size. The Stratix GX FPGA technology is built upon the Stratix
architecture, and offers a 1.5-V logic array with unmatched performance,
flexibility, and time-to-market capabilities. This scalable,
high-performance architecture makes Stratix GX devices ideal for
high-speed backplane interface, chip-to-chip, and communications
protocol-bridging applications.
Transceiver block features are as follows:
Features
High-speed serial transceiver channels with CDR provides
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
Devices are available with 4, 8, 16, or 20 high-speed serial
transceiver channels providing up to 127.5 Gbps of full-duplex
serial bandwidth
Support for transceiver-based protocols, including 10 Gigabit
Ethernet attachment unit interface (XAUI), Gigabit Ethernet
(GigE), and SONET/SDH
Compatible with PCI Express, SMPTE 292M, Fibre Channel, and
Serial RapidIO I/O standards
Programmable differential output voltage (V ), pre-emphasis,
OD
and equalization settings for improved signal integrity
Individual transmitter and receiver channel power-down
capability implemented automatically by the Quartus II
software for reduced power consumption during non-operation
Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, and 20-bit wide data paths
1.5-V pseudo current mode logic (PCML) for 500 Mbps to
3.1875 Gbps
Support for LVDS, LVPECL, and 3.3-V PCML on reference
clocks and receiver input pins (AC-coupled)
Built-in self test (BIST)
Hot insertion/removal protection circuitry
Altera Corporation 1
DS-STXGX-2.2 PreliminaryStratix GX FPGA Family
Pattern detector and word aligner supports programmable
patterns
8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-
to 8-bit decoding
Rate matcher compliant with IEEE 802.3-2002 for GigE mode
and with IEEE 802-3ae for XAUI mode
Channel bonding compliant with IEEE 802.3ae (for XAUI mode
only)
Device can bypass some transceiver block features if necessary
FPGA features are as follows:
10,570 to 41,250 logic elements (LEs); see Table 1
Up to 3,423,744 RAM bits (427,968 bytes) available without
reducing logic resources
TriMatrix memory consisting of three RAM block sizes to
implement true dual-port memory and first-in-out (FIFO)
buffers
Up to 16 global clock networks with up to 22 regional clock
networks per device region
High-speed DSP blocks provide dedicated implementation of
multipliers (faster than 300 MHz), multiply-accumulate
functions, and finite impulse response (FIR) filters
Up to eight general usage phase-locked loops (four enhanced
PLLs and four fast PLLs) per device provide spread spectrum,
programmable bandwidth, clock switchover, real-time PLL
reconfiguration, and advanced multiplication and phase
shifting
Support for numerous single-ended and differential I/O
standards
High-speed source-synchronous differential I/O support on up
to 45 channels for 1-Gbps performance
Support for source-synchronous bus standards, including
10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,
TM
Network Packet Streaming Interface (NPSI), HyperTransport
technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)
SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM
(FCRAM), and single data rate (SDR) SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore functions and Altera Megafunction Partners
SM
Program (AMPP ) megafunctions
Support for remote configuration updates
Dynamic phase alignment on LVDS receiver channels
2 Altera Corporation
Preliminary