APEX 20K
Programmable Logic
Device Family
March 2004, ver. 5.1 Data Sheet
Industrys first programmable logic device (PLD) incorporating
Features
system-on-a-programmable-chip (SOPC) integration
TM
MultiCore architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
High density
30,000 to 1.5 million typical gates (see Tables 1 and 2)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features Note (1)
Feature EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E
Maximum 113,000 162,000 263,000 263,000 404,000 526,000 526,000
system
gates
Typical 30,000 60,000 100,000 100,000 160,000 200,000 200,000
gates
LEs 1,200 2,560 4,160 4,160 6,400 8,320 8,320
ESBs 12 16 26 26 40 52 52
Maximum 24,576 32,768 53,248 53,248 81,920 106,496 106,496
RAM bits
Maximum 192 256 416 416 640 832 832
macrocells
Maximum 128 196 252 246 316 382 376
user I/O
pins
Altera Corporation 1
DS-APEX20K-5.1APEX 20K Programmable Logic Device Family Data Sheet
Table 2. Additional APEX 20K Device Features Note (1)
Feature EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
Maximum system 728,000 1,052,000 1,052,000 1,537,000 1,772,000 2,392,000
gates
Typical gates 300,000 400,000 400,000 600,000 1,000,000 1,500,000
LEs 11,520 16,640 16,640 24,320 38,400 51,840
ESBs 72 104 104 152 160 216
Maximum 147,456 212,992 212,992 311,296 327,680 442,368
RAM bits
Maximum 1,152 1,664 1,664 2,432 2,560 3,456
macrocells
Maximum user I/O 408 502 488 588 708 808
pins
Note to Tables 1 and 2:
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
Designed for low-power operation
Additional
1.8-V and 2.5-V supply voltage (see Table 3)
TM
Features
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
ESB offering programmable power-saving mode
Table 3. APEX 20K Supply Voltages
Feature Device
EP20K100 EP20K30E
EP20K200 EP20K60E
EP20K400 EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Internal supply voltage (V ) 2.5 V 1.8 V
CCINT
MultiVolt I/O interface voltage levels (V ) 2.5 V, 3.3 V, 5.0 V 1.8 V, 2.5 V, 3.3 V, 5.0 V (1)
CCIO
Note to Table 3:
(1) APEX 20KE devices can be 5.0-V tolerant by using an external resistor.
2 Altera Corporation