APEX 20KC Programmable Logic Device February 2004 ver. 2.2 Data Sheet Programmable logic device (PLD) manufactured using a 0.15-m all- Features... layer copper-metal fabrication process TM 25 to 35% faster design performance than APEX 20KE devices Pin-compatible with APEX 20KE devices High-performance, low-power copper interconnect TM MultiCore architecture integrating look-up table (LUT) logic and embedded memory LUT logic used for register-intensive functions Embedded system blocks (ESBs) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM) High-density architecture 200,000 to 1 million typical gates (see Table 1) Up to 38,400 logic elements (LEs) Up to 327,680 RAM bits that can be used without reducing available logic Table 1. APEX 20KC Device Features Note (1) Feature EP20K200C EP20K400C EP20K600C EP20K1000C Maximum system gates 526,000 1,052,000 1,537,000 1,772,000 Typical gates 200,000 400,000 600,000 1,000,000 LEs 8,320 16,640 24,320 38,400 ESBs 52 104 152 160 Maximum RAM bits 106,496 212,992 311,296 327,680 PLLs (2) 2444 Speed grades (3) -7, -8, -9 -7, -8, -9 -7, -8, -9 -7, -8, -9 Maximum macrocells 832 1,664 2,432 2,560 Maximum user I/O pins 376 488 588 708 Notes to Table 1: (1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 57,000 additional gates. (2) PLL: phase-locked loop. (3) The -7 speed grade provides the fastest performance. Altera Corporation 1 DS-APEX20KC-2.2APEX 20KC Programmable Logic Device Data Sheet Low-power operation design ...and More 1.8-V supply voltage (see Table 2) Features Copper interconnect reduces power consumption TM MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces ESBs offering programmable power-saving mode Flexible clock management circuitry with up to four phase-locked loops (PLLs) Built-in low-skew clock tree Up to eight global clock signals TM ClockLock feature reducing clock delay and skew TM ClockBoost feature providing clock multiplication and division TM ClockShift feature providing programmable clock phase and delay shifting Powerful I/O features Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits Support for high-speed external memories, including DDR synchronous dynamic RAM (SDRAM) and ZBT static RAM (SRAM) 16 input and 16 output LVDS channels at 840 megabits per second (Mbps) Direct connection from I/O pins to local interconnect providing fast t and t times for complex logic CO SU MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces Programmable clamp to V CCIO Individual tri-state output enable control for each pin Programmable output slew-rate control to reduce switching noise Support for advanced I/O standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I Supports hot-socketing operation Pull-up on I/O pins before and during configuration Table 2. APEX 20KC Supply Voltages Feature Voltage Internal supply voltage (V ) 1.8 V CCINT MultiVolt I/O interface voltage levels (V ) 1.8 V, 2.5 V, 3.3 V, 5.0 V (1) CCIO Note to Table 2: (1) APEX 20KC devices can be 5.0-V tolerant by using an external resistor. 2 Altera Corporation