1. Introduction CII51001-3.2 Following the immensely successful first-generation Cyclone device Introduction family, Altera Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMC s 90-nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who compromise power consumption and performance for low-cost, Alteras latest generation of low-cost FPGAsCyclone II FPGAs, offer 60% higher performance and half the power consumption of competing 90-nm FPGAs. The low cost and optimized feature set of Cyclone II FPGAs make them ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions. Reference designs, system diagrams, and IP, found at www.altera.com, are available to help you rapidly develop complete end-market solutions using Cyclone II FPGAs. Low-Cost Embedded Processing Solutions Cyclone II devices support the Nios II embedded processor which allows you to implement custom-fit embedded processing solutions. Cyclone II devices can also expand the peripheral set, memory, I/O, or performance of embedded processors. Single or multiple Nios II embedded processors can be designed into a Cyclone II device to provide additional co-processing power or even replace existing embedded processors in your system. Using Cyclone II and Nios II together allow for low-cost, high-performance embedded processing solutions, which allow you to extend your product s life cycle and improve time to market over standard product solutions. Low-Cost DSP Solutions Use Cyclone II FPGAs alone or as DSP co-processors to improve price-to-performance ratios for digital signal processing (DSP) applications. You can implement high-performance yet low-cost DSP systems with the following Cyclone II features and design support: Up to 150 18 18 multipliers Up to 1.1 Mbit of on-chip embedded memory High-speed interfaces to external memory Altera Corporation 11 February 2008Features DSP intellectual property (IP) cores DSP Builder interface to The Mathworks Simulink and Matlab design environment DSP Development Kit, Cyclone II Edition Cyclone II devices include a powerful FPGA feature set optimized for low-cost applications including a wide range of density, memory, embedded multiplier, and packaging options. Cyclone II devices support a wide range of common external memory interfaces and I/O protocols required in low-cost applications. Parameterizable IP cores from Altera and partners make using Cyclone II interfaces and protocols fast and easy. The Cyclone II device family offers the following features: Features High-density architecture with 4,608 to 68,416 LEs M4K embedded memory blocks Up to 1.1 Mbits of RAM available without reducing available logic 4,096 memory bits per block (4,608 bits per block including 512 parity bits) Variable port configurations of 1, 2, 4, 8, 9, 16, 18, 32, and 36 True dual-port (one read and one write, two reads, or two writes) operation for 1, 2, 4, 8, 9, 16, and 18 modes Byte enables for data input masking during writes Up to 260-MHz operation Embedded multipliers Up to 150 18- 18-bit multipliers are each configurable as two independent 9- 9-bit multipliers with up to 250-MHz performance Optional input and output registers Advanced I/O support High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces PCI Express with an external TI PHY and an Altera PCI Express 1 Megacore function 12 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2008