1. Cyclone III Device Family Overview July 2012 CIII51001-2.4 CIII51001-2.4 Cyclone III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants: Cyclone IIIlowest power, high functionality with the lowest cost Cyclone III LSlowest power FPGAs with security With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application. This chapter contains the following sections: Cyclone III Device Family Features on page 11 Cyclone III Device Family Architecture on page 16 Reference and Ordering Information on page 112 Cyclone III Device Family Features Cyclone III device family offers the following features: Lowest Power FPGAs Lowest power consumption with TSMC low-power process technology and Altera power-aware design flow Low-power operation offers the following benefits: Extended battery life for portable and handheld applications Reduced or eliminated cooling system costs Operation in thermally-challenged environments Hot-socketing operation support 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as ISO trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its 9001:2008 semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and Registered services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Cyclone III Device Handbook Volume 1 July 2012 Subscribe12 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Features Design Security Feature Cyclone III LS devices offer the following design security features: Configuration security using advanced encryption standard (AES) with 256-bit volatile key Routing architecture optimized for design separation flow with the Quartus II software Design separation flow achieves both physical and functional isolation between design partitions Ability to disable external JTAG port Error Detection (ED) Cycle Indicator to core Provides a pass or fail indicator at every ED cycle Provides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits Ability to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key Internal oscillator enables system monitor and health check capabilities Increased System Integration High memory-to-logic and multiplier-to-logic ratio High I/O count, low-and mid-range density devices for user I/O constrained applications Adjustable I/O slew rates to improve signal integrity Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS Supports the multi-value on-chip termination (OCT) calibration feature to eliminate variations over process, voltage, and temperature (PVT) Four phase-locked loops (PLLs) per device provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces Five outputs per PLL Cascadable to save I/Os, ease PCB routing, and reduce jitter Dynamically reconfigurable to change phase shift, frequency multiplication or division, or both, and input frequency in the system without reconfiguring the device Remote system upgrade without the aid of an external controller Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues Nios II embedded processor for Cyclone III device family, offering low cost and custom-fit embedded processing solutions Cyclone III Device Handbook July 2012 Altera Corporation Volume 1